fpga config mcu

This software is running on the STM32F103C8 on the Data Processor Board.

SPI Flash Memory Map

The main purpose of the SPI Flash is to store different configuration bit files for the FPGA. Bit files can vary in size depending on if compression is enabled or not but the largest possible size for the FPGA currently used (EP4CE10) is 2 944 088 bits = 368 011 bytes.

The SPI Flash (S25FL116K0XMFI011) has this memory organization:

32 blocks with 64 kbytes in each
512 sectors with 4 kbytes in each
8192 pages with 256 bytes in each

This means 1 block = 16 sectors = 256 pages

Erase commands can be done on the full chip, a block or a sector. We therefore have to align the bit files so that it's easy to erase them separately. One bit file takes up 368011/(64*1024) = 5,6154... blocks ≈ 6 blocks. If we assign 6 blocks for each bit file we should get the best erase performance.

A memory map of the SPI Flash can be seen below.

Block	Sector	Page	Startaddress (Hex)	Content
0	0	0	0x00000000	reserved

| - | - | - | - 6 | 96 | 1536 | 0x00060000 | FPGA Bit File 1 Header 6 | 96 | 1537 | 0x00060100 | FPGA Bit File 1 Data Start
| - | - | - | - 12 | 192 | 3072 | 0x000C0000 | FPGA Bit File 2 Header 12 | 192 | 3073 | 0x000C0100 | FPGA Bit File 2 Data Start
| - | - | - | - 18 | 288 | 4608 | 0x00120000 | FPGA Bit File 3 Header 18 | 288 | 4609 | 0x00120100 | FPGA Bit File 3 Data Start
| - | - | - | - 24 | 384 | 6144 | 0x00180000 | FPGA Bit File 4 Header 24 | 384 | 6145 | 0x00180100 | FPGA Bit File 4 Data Start
| - | - | - | - 30 | 480 | 7680 | 0x001E0000 | FPGA Bit File 5 Header 30 | 480 | 7681 | 0x001E0100 | FPGA Bit File 5 Data Start
| - | - | - | - 31 | 511 | 8192 | 0x00200000 | Last page on SPI Flash

FPGA Bit File Header

Byte[0:3]: 32-bit number with the size of the bit file. This is checked before reading a bit file in memory to make sure it's a valid bit file.
Byte[4:67]: 64-bytes of filename as ASCII characters
Byte[68]: Year of bitfile modification (unsigned: 0-99)
Byte[69]: Month of bitfile modification (unsigned: 0-12)
Byte[70]: Day of bitfile modification (unsigned: 0-31)
Byte[71]: Hour of bitfile modification (unsigned: 0-23)
Byte[72]: Minute of bitfile modification (unsigned: 0-59)
Byte[73]: Second of bitfile modification (unsigned: 0-59)
Byte[74:89]: MD5 checksum of the bitfile

UART1 Communication

The UART1 can be used to write bit files to the SPI Flash or to configure the FPGA. Baudrate: 115200

Command Structure:

The basic structure of a command is: [0xAA, 0xBB, 0xCC, (1 byte command), (2 byte data count), (data), (1 byte checksum)]. Where 0xAA, 0xBB, 0xCC is a header to detect the start of a transmission. The config MCU will either respond with an ACK (0xDD), a NACK (0xEE) or unknown command (0xDE).

Checksum:

To make sure the communication is a bit more reliable there is a checksum byte at the end of a transmission. It is calculated as a bytewise-XOR between all bytes in the message, i.e. 0xAA ^ 0xBB ^ 0xCC ^ (command) ^ (data count) ^ (data).

Available Commands:

Value	Command	Data	Return Value
0x10	SET FLASH WRITE ADDRESS	4 bytes write address to save	None
0x11	GET FLASH WRITE ADDRESS	None	4 byte write address MSByte first
0x20	ERASE FULL FLASH	None	None
0x21	ERASE SECTOR IN FLASH	4 bytes address for sector to erase	None
0x22	ERASE FPGA BIT FILE	1 byte number of the bit file	None
0x30	WRITE DATA TO FLASH	The data to write, 0 to 512 bytes	None
0x40	READ DATA FROM FLASH	4 bytes read address, 1 byte num of bytes to read	Data read
0x50	START FPGA CONFIG	1 byte number of the bit file to config with	None

Example commands:

Set write address to 0x00000000: AA BB CC 10 00 04 00 00 00 00 C9
Set write address to 0x11223344: AA BB CC 10 00 04 11 22 33 44 8D
Get current write address: AA BB CC 11 CC
Erase full flash: AA BB CC 20 FD
Erase first sector at 0x00000000: AA BB CC 21 00 04 00 00 00 00 F8
Write "Hello World" to flash: AA BB CC 30 00 0B 48 65 6C 6C 6F 20 57 6F 72 6C 64 C6
Read 11 bytes from flash at address 0x00000000: AA BB CC 40 00 05 00 00 00 00 0B 93
Read 256 bytes from flash at address 0x00000000: AA BB CC 40 00 05 00 00 00 00 FF 67