FPGA Timestamp
The timestamp is used to put a timestamp on the data that is saved to memory. Internally it's basically a 32-bit counter that is counting up when it is activated.
Resolution of the timer inside the timestamp can be changed in order to allow the user greater control of the information stored. The following resolutions can be set:
- 1ms: 4294967296ms max ≈ 1193 hours max
- 100us: 429496729600us max ≈ 119.3 hours max
- 10us: 42949672960us max ≈ 11.9 hours max
- 1us: 4294967296us max ≈ 71.6 minutes ≈ 1.2 hours max
- 100ns: 429496729600ns max ≈ 429.5 seconds ≈ 7.16 minutes
When an overflow happens the counter will start from 0 again. This will be seen in the displayed data as data first having a high timestamp and then the next data having a low (or zero) timestamp.
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Version 2:
ui-processor-rtos
fpga-config-mcu
fpga-config-over-uart
Version 1:
freertos-serial-monitor
freertos-serial-monitor lcd test
Simple GUI:
General
GUIObject
GUIButton
GUILabel
GUIStaticTextBox
GUIAlertBox
GUIButtonGridBox
GUIButtonList
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Tasks:
LCD Task Message
LCD:
LCD ER-TFT070-4
LCD ER-TFTM070-5
LCD HY070CTP-HD
LCD HY101CTP-HD
LCD YL070MY01
Touch Controller
Measurements:
STM32 GPIO Speed
FT5206 Waveform Capture
Version 2:
Revision 2 Mockup
Module IDs
Boards:
Connection Board
UI Processor Board
Data Processor Board
Isolated Power Module
LCD Board
Modules:
1. GPIO Module
3. CAN Module
5. RS-232 Module
15. nRF24L01 Module
Future Module Ideas
FPGA:
FPGA Main Blocks
FPGA Communication
FPGA UART
FPGA GPIO
FPGA Timestamp
FPGA SDRAM
FPGA PLL
[FPGA ID Reader](https://github.com/hampussandberg/HexConnect/wiki/FPGA-ID Reader)
FPGA LVDS
FPGA Monitor
FPGA Tips and Tricks
Learning Quartus II
Version 1:
Requirement Specification
Hardware Design
Hardware Rev 1 Fixes