Hardware Rev1 Fixes
- Connect the crystals to the correct pins, is reversed i rev 1
- Remove power relays for UART channels and set 3.3V as default. Add a 5V tolerant buffer on the RX and TX pins to the connector.
- Replace relays with mux/DPST analog switch ?
- Look for CME0505 replacement -> they have bad spec for low load!
- Remove the extra mounting holes?
- Supply voltage for CAN isolators on non-isolated side should be 3.3V
- V_IO on TJA1051T/3 should be connected to respective isolated voltage as this pin sets the IO voltage. Was disconnected on rev 1. Change to a different CAN transceiver or fix this!
- Switch to SSD1963 screen + STM32F429/STM32F427. Video1, Video2, Video3. Or use raw RGB screen and tft controller of STM32
Homepage
Pictures
GUI Mockup
Contact
Version 2:
ui-processor-rtos
fpga-config-mcu
fpga-config-over-uart
Version 1:
freertos-serial-monitor
freertos-serial-monitor lcd test
Simple GUI:
General
GUIObject
GUIButton
GUILabel
GUIStaticTextBox
GUIAlertBox
GUIButtonGridBox
GUIButtonList
GUIInfoBox
Tasks:
LCD Task Message
LCD:
LCD ER-TFT070-4
LCD ER-TFTM070-5
LCD HY070CTP-HD
LCD HY101CTP-HD
LCD YL070MY01
Touch Controller
Measurements:
STM32 GPIO Speed
FT5206 Waveform Capture
Version 2:
Revision 2 Mockup
Module IDs
Boards:
Connection Board
UI Processor Board
Data Processor Board
Isolated Power Module
LCD Board
Modules:
1. GPIO Module
3. CAN Module
5. RS-232 Module
15. nRF24L01 Module
Future Module Ideas
FPGA:
FPGA Main Blocks
FPGA Communication
FPGA UART
FPGA GPIO
FPGA Timestamp
FPGA SDRAM
FPGA PLL
[FPGA ID Reader](https://github.com/hampussandberg/HexConnect/wiki/FPGA-ID Reader)
FPGA LVDS
FPGA Monitor
FPGA Tips and Tricks
Learning Quartus II
Version 1:
Requirement Specification
Hardware Design
Hardware Rev 1 Fixes