LCD ER_TFTM070_5
The whole project started when I was searching on eBay after TFT LCDs with capacitive touch and found a company called BuyDisplay with a lot of different displays for sale. They had two 7-inch displays with a capacitive touch panel as an option and I choose the one using the RA8875 controller, link to the display. They also have one with the SSD1963 controller but I didn't see that one before my order was placed, link to the SSD1963 display.
I placed an order for one display on april 27 and received it on may 26 and it was sent from the BuyDisplay on may 7. Worth to note is that I picked the cheapest shipping they had, but they also offer faster shipping which probably is better to choose if you order more than one display at the same time.
Here are some images of the display I received:
Front of display
Back of display
Date code of display
It's alive!
To get the fastest frame update as possible the parallell 16-bit 8080 interface was chosen. There are a couple of jumpers on the LCD board which has to be set or removed in order to select the interface but all the information is available in the datasheet. The STM32F407VG microcontroller used has a FSMC interface which can be setup to interface to 16-bit 8080 as detailed in the AN2790 application note. The app note is for the STM32F1 series but the connections is the same for the F4-series.
The following table can be found in the reference manual rev 7 on page 1528 which describe the parameters you can set for the FSMC interface.
| Parameter | Function | Unit | Min. | Max. |
|---|---|---|---|---|
| Address setup | Duration of the address setup phase | AHB clock cycle (HCLK) | 0 | 15 |
| Address hold | Duration of the address hold phase | AHB clock cycle (HCLK) | 1 | 15 |
| Data setup | Duration of the data setup phase | AHB clock cycle (HCLK) | 1 | 256 |
| Bust turn | Duration of the bus turnaround phase | AHB clock cycle (HCLK) | 0 | 15 |
| Clock divide ratio | Number of AHB clock cycles (HCLK) to build one memory clock cycle (CLK) | AHB clock cycle (HCLK) | 2 | 16 |
| Data latency | Number of clock cycles to issue to the memory before the first data of the burst | Memory clock cycle (CLK) | 2 | 17 |
Table 1. FSMC Parameters
To calculate these values you need, according to the AN2790 application note, the following values found on page 58 in the datasheet for the RA8875 controller:
| Symbol | Parameter | Value |
|---|---|---|
| t_AH | Address hold time | 10 ns |
| t_AS | Address setup time | 0 ns |
| t_CYC | System cycle time | 50 ns (1/SYS_CLK) |
| t_CYC(READ) | System cycle time (Read) | 50 ns (1/SYS_CLK) |
| t_WRLW | Low pulse width for write | 20 ns (Strobe Pulse width) |
| t_WRLR | Low pulse width for read | 20 ns (Strobe Pulse width) |
| t_WRHW | High pulse width for write | 20 ns (Strobe Pulse width) |
| t_WRHR | High pulse width for read | 20 ns (Strobe Pulse width) |
| t_DS | Data setup time | 20 ns |
| t_DH | Data hold time | 20 ns |
| t_ACC | Data access time | 20 ns maximum |
Table 2. LCD Characteristics
The application note says: "Usually, ModeB is used for LCD interfacing (so the extended mode is not used) and the same timings are used for read and write operations." We therefore only need to calculate three of the parameters in Table 1: ADDSET, DATAST and ADDHOLD (the abbrevations should hopefully be logical). These parameters are calculated according to the LCD characteristics and as a function of the STM32F407 AHB clock (HCLK), f_HCLK = 168 MHz. The equations in the AN2790 app note looks a bit strange but luckily they look better in the AN2784 App Note which is also referenced from here. The equations are:
- ((ADDSET + 1) + (DATAST + 1)) * t_HCLK ≥ max(t_WC)
- DATAST * t_HCLK = t_WP
- DATAST ≥ (t_AVQV + t_su(Data_NE) + t_v(A_NE))/t_HCLK - ADDSET - 4
With the following definitions and values for the symbols:
| Symbol | Parameter | Value |
|---|---|---|
| t_WC | Address valid to next address valid for write operation (write cycle time) | 50 ns (1/SYS_CLK) |
| t_WP | Write Enable low to Write Enable high (Write Enable low pulse width) | 20 ns (Strobe Pulse width) |
| t_AVQV | Address valid to output valid | 20 ns |
| t_HCLK | Internal AHB clock cycle | 1/168 MHz ≈ 5.95 ns |
| t_su(Data_NE) | Data to FSMC_NEx high setup time | t_HCLK + 4 = 9.95 ns |
| t_v(A_NE) | FSMC_NEx low to FSMC_A valid | 0 ns (not sure about this one but the app note use the one which is 0) |
Table 3. Symbols used in equations
Equation 2: DATAST = t_WP/t_HCLK = 20/5.95 = 3.36 ≈ 3
Equation 1: ADDSET ≥ max(t_WC)/t_HCLK - ((ADDSET + 1) - 1 = 50/5.95 - (3+1) - 1 ≈ 3.40 -> ADDSET = 4
Equation 3: DATAST ≥ ((20 + 9.95 + 0)/5.95 - 4 - 4 ≈ -2.97 -> Should be OK!
Our parameters are: DATAST = 3 and ADDSET = 4. Note that in AN2784 they don't mention ADDHOLD so I assume we can set it to whatever valid value we want.
Now that FSMC is setup the principle should be that by writing to a certain address on the MCU we are actually writing to the external memory (in this case the LCD). On page 1523 in figure 433 in the reference manual it shows the address to where we should write/read. They call that address HADDR and it consists of these parts:
FSMC HADDR bit explanation
This gives us two addresses we can use to communicate with the LCD:
- 0x60080000 - For commands
- 0x60000000 - For data
Datasheet for the controller can be found here
RA8875 Controller on the LCD
The RA8875 controller have a block transfer engine which is used for sending blocks of data to be displayed. In the image below 800*480 = 384 000 16-bit values are sent over the parallell port using the BTE.
Displaying an image using the BTE on RA8875
The LCD module is using the FT5206 IC (datasheet) for the capacitive touch panel.
FT5206 on the LCD
A good thing about this LCD is that one can choose a resistive touch panel as well. To interface with the resistive touch panel one simply send some commands to the RA8875 controller which has built in support for this type of panel. It will therefore not require any change in the hardware, only some extra software.