FPGA PLL
On the board there is a 50 MHz oscillator but inside we would like to use a higher frequency of 100 MHz. This is done by using one of the two available PLLs inside the Cyclone IV E FPGA.
Page 83 (5-21) in Cyclone IV Handbook
Page 85 (5-23) in Cyclone IV Handbook
Warning: PLL "pll:pll|altpll:altpll_component|pll_altpll1:auto_generated|pll1" is in normal or source synchronous mode with output clock "compensate_clock" set to clk[0] that is not fully compensated because it feeds an output pin -- only PLLs in zero delay buffer mode can fully compensate output pins
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Version 2:
ui-processor-rtos
fpga-config-mcu
fpga-config-over-uart
Version 1:
freertos-serial-monitor
freertos-serial-monitor lcd test
Simple GUI:
General
GUIObject
GUIButton
GUILabel
GUIStaticTextBox
GUIAlertBox
GUIButtonGridBox
GUIButtonList
GUIInfoBox
Tasks:
LCD Task Message
LCD:
LCD ER-TFT070-4
LCD ER-TFTM070-5
LCD HY070CTP-HD
LCD HY101CTP-HD
LCD YL070MY01
Touch Controller
Measurements:
STM32 GPIO Speed
FT5206 Waveform Capture
Version 2:
Revision 2 Mockup
Module IDs
Boards:
Connection Board
UI Processor Board
Data Processor Board
Isolated Power Module
LCD Board
Modules:
1. GPIO Module
3. CAN Module
5. RS-232 Module
15. nRF24L01 Module
Future Module Ideas
FPGA:
FPGA Main Blocks
FPGA Communication
FPGA UART
FPGA GPIO
FPGA Timestamp
FPGA SDRAM
FPGA PLL
[FPGA ID Reader](https://github.com/hampussandberg/HexConnect/wiki/FPGA-ID Reader)
FPGA LVDS
FPGA Monitor
FPGA Tips and Tricks
Learning Quartus II
Version 1:
Requirement Specification
Hardware Design
Hardware Rev 1 Fixes