FPGA LVDS

Four LVDS channels are used for communication between the FPGA on the Data Processor Board and the MCU on the UI Processor Board. This is in fact an SPI bus that is converted to LVDS to try to minimize any EMC issues.

VCCIO issue

On page 6-12 (table 6-3) in the Cyclone IV handbook it says that the VCCIO level when using the LVDS interface should be 2.5V. Originally I had set all VCCIOs to 3.3V for simplicity but fortunately Quartus gave an error indicating that you could not mix 3.3V interface pins with LVDS pins.

The LVDS pins I'm using are located on bank 1 and 2. On these banks I also have two LEDs and an SPI bus for communicating with the config MCU. The LEDs would probably work on 2.5V as well but they were easy to move to bank 8 instead. The SPI bus could also be moved easily to bank 3.

After a quick look at the various input/output levels of the MCU and FPGA I think it would have worked to have the SPI bus running on 2.5V but I think it looks nicer to have it on 3.3V and keeping bank 1 and 2 for the LVDS signals.

TODO: Config SPI bus still on 2.5V, explain why it should work