Learning Quartus II

As I'm using the DE0-Nano development board which has an Altera FPGA on it I chose to use their development environment, Quartus II, as well. Here are some things I've learned about it.

Creating a symbol file from a block diagram / schematic

If you want to use a block diagram as a part of another block diagram you have to create a symbol for it. This can be done by opening the block diagram and then choosing File -> Create/Update -> Create Symbol Files For Current File.

Altera FIFO MegaFunction and floating pins

See below for the solution.
While trying to put some of the small parts of the design together into the final top-level design I came across an error when trying to compile. Basically what it says that at the top-level there are some inputs (physical pins on the FPGA) that with the design hierarchy that I have is not driving anything and therefore the compiler will optimize away the design completely. That's of course what I want! The error message is quite clear but finding where in the design the signal is cut off is proving to be harder.

I think I found where the problem is by following the input signal and checking if each block in the signal path is affected by the signal by placing an output port at one of the relevant outputs of the block. By setting an output port it seems that we are forcing the block to be active and therefore making sure the input signal is driving logic. By doing this and going down in the design I came to a block where I think the problem is located.

This block is connected to a FIFO block which is generated using a MegaFunction in Quartus. I'm also getting some error messages saying "Output pins are stuck at VCC or GND" and some of those pins are from the FIFO block.

SOLUTION: After many hours of trying to find which block was not working as it should I found the problem and a solution. It didn't really have anything to do with what I wrote about earlier, the problem was that I didn't connect the "rdreq" (read request) on the FIFO to anything that will at some point drive it HIGH. This makes the compiler think that we will never read anything from the FIFO and therefore it thinks that it can optimize it away. This makes sense I guess as there's no point saving data if you don't want to read it later.

The main error I did was to try using the FIFO "halfway", i.e. only for saving data because I wanted to test that part first. But the compiler is too smart and removes it all together.

LESSON: Always make sure inputs to a block are set up properly so that all parts of the block will function, otherwise the compiler will optimize away things from it. This can be done temporarily by connecting the input to an "input pin object" in Quartus and setting the pins default value to VDD or GND. IMPORTANT: You have to propagate this input pin object all the way up to the top-level entity.

Pin-Out File

After assigning all the signals in the design and compiling a Pin-Out file will be created. Some things in this file is worth noting:

• Pins marked GND+ should be connected to GND on the PCB

Bit concatenation

If we have an output signal out[4..0] and want to assign this to an input in[7..0] we can't connect them directly as the width is not matching. In Quartus you can use a small trick to fix this. The signal that goes to the input can be named (0,0,0,out[4...0]) which will give the correct width with the top 3 bits set to 0.