ncnn is a high-performance neural network inference framework optimized for the mobile platform

Capstone disassembly/disassembler framework for ARM, ARM64 (ARMv8), Alpha, BPF, Ethereum VM, HPPA, M68K, M680X, Mips, MOS65XX, PPC, RISC-V(rv32G/rv64G), SH, Sparc, SystemZ, TMS320C64X, TriCore, Webassembly, XCore and X86.

Unicorn CPU emulator framework (ARM, AArch64, M68K, Mips, Sparc, PowerPC, RiscV, S390x, TriCore, X86)

Rocket Chip Generator

Tengine is a lite, high performance, modular inference engine for embedded device

An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more

MicroPython for K210 RISC-V, let's play with edge AI easier

SonicBOOM: The Berkeley Out-of-Order Machine

A FPGA friendly 32 bit RISC-V CPU implementation

CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform

Rust version of THU uCore OS. Linux compatible.

The Ultra-Low Power RISC-V Core

A debugging toolset and library for debugging embedded ARM and RISC-V targets on a separate host

opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

SCR1 is a high-quality open-source RISC-V MCU core in Verilog

Sunflower Full-System Hardware Emulator and Physical System Simulator for Sensor-Driven Systems. Built-in architecture modeling of Hitachi SH (j-core), RISC-V, and more.

RARS -- RISC-V Assembler and Runtime Simulator

World Of Warcraft 3.3.5a server

VeeR EH1 core

🚀 A tiny, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.