Here are
34 public repositories
matching this topic...
A FPGA friendly 32 bit RISC-V CPU implementation
Updated
Apr 4, 2024
Assembly
CNN accelerator implemented with Spinal HDL
Updated
Jan 29, 2024
Scala
A reimplementation of a tiny stack CPU
Updated
Dec 8, 2023
Scala
High performance LA32R out-of-order processor core. (NSCSCC 2023 Special Prize)
Updated
Aug 29, 2023
Scala
[HPCA'21] SpAtten: Efficient Sparse Attention Architecture with Cascade Token and Head Pruning
Updated
May 3, 2024
Scala
SpinalHDL - Cryptography libraries
Updated
Oct 30, 2022
Scala
Translated SpinalHDL-Doc(v1.7.2) into Chinese
Updated
Jun 11, 2023
HTML
A re-creation of a Cosmac ELF computer, Coded in SpinalHDL
Updated
Apr 23, 2021
VHDL
The SpinalHDL design of the Proteus core, an extensible RISC-V core.
Updated
May 8, 2024
Scala
Wrappers for open source FPU hardware implementations.
Updated
Apr 10, 2024
Verilog
shdl6800: A 6800 processor written in SpinalHDL
Updated
Jan 12, 2020
Scala
The sources of the online SpinalHDL doc
Updated
May 3, 2024
Python
Docker Development Environment for SpinalHDL
Updated
May 30, 2020
Dockerfile
CNN accelerator implemented with Spinal HDL
Updated
Dec 27, 2021
Scala
Updated
Mar 13, 2017
Forth
Matrix Multiplication in Hardware
A classic 5-stage rv32i(incomplete) toy implementation based on powerful SpinalHDL
Updated
Jul 5, 2021
Scala
Reusable small hardware components for SpinalHDL
Updated
Apr 11, 2023
Scala
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