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Syntacore

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scr1 scr1 Public

SCR1 is a high-quality open-source RISC-V MCU core in Verilog

SystemVerilog 776 264
scr1-sdk scr1-sdk Public

open-source SDKs for the SCR1 core

C 65 31

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Showing 10 of 39 repositories

snippy Public

21 4 13 (1 issue needs help) 1 Updated May 7, 2024
scr1-sdk Public
open-source SDKs for the SCR1 core

C 65 31 0 0 Updated May 7, 2024
scr1 Public
SCR1 is a high-quality open-source RISC-V MCU core in Verilog

SystemVerilog 776 264 3 (2 issues need help) 2 Updated May 6, 2024
linux Public

C 2 1 0 0 Updated Mar 11, 2024
syntaj21 Public Forked from openjdk/jdk21u
https://openjdk.org/projects/jdk-updates

Java 0 GPL-2.0 116 0 0 Updated Jan 24, 2024
zephyr Public Forked from zephyrproject-rtos/zephyr
Primary GIT Repository for the Zephyr Project

C 1 Apache-2.0 6,011 0 0 Updated Nov 14, 2023
syntaj17 Public

Java 1 GPL-2.0 0 0 0 Updated Feb 9, 2023
riscv-binutils-gdb Public Forked from riscvarchive/riscv-binutils-gdb
RISC-V port of GDB

C 3 GPL-2.0 233 0 0 Updated Dec 21, 2022
opensbi Public

C 1 0 0 0 Updated Dec 14, 2022
qemu Public

0 0 0 0 Updated Dec 12, 2022

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