The RISC-V Virtual Machine

VeeR EH1 core

Compact and Efficient RISC-V RV32I[MAFC] emulator

Simple unix-like operating system for education and research purposes

F# RISC-V Instruction Set formal specification

VeeR EL2 Core

Running Linux on RP2040 with the help of RISC-V emulation

UART based embedded shell for embedded systems. Intended to be used for learning, experimenting and diagnostics.

💻 RISC-V Simulator of RV32I ISA. 5-stage pipeline / out-of-order execution with Tomasulo algorithm and Speculation. Support runtime visualization. Project report available.

Simple risc-v emulator, able to run linux, written in C.

😎 A curated list of awesome RISC-V implementations

A RISC-V 5-stage pipelined CPU that supports vector instructions. Tape-out with U18 technology.

An AXI4 crossbar implementation in SystemVerilog

Yet Another RISC-V Implementation

Instruction set simulator for RISC-V, MIPS and ARM-v6m

An interpreter for a concurrent lisp-like language with message-passing and pattern-matching implemented in C.

Lower level assembly and C baremetal programming on RISC-V CPUs. Source code listings from the C-Ninja, in Pyjama! book.

A c/RISCV of "Let's Build a Compiler" by Jack Crenshaw

TinyFive is a lightweight RISC-V emulator and assembler written in Python with neural network examples

A model of the RISC Zero zkVM and ecosystem in the Lean 4 Theorem Prover