Skip to content
View stnolting's full-sized avatar
🦸
just your average ordinary everyday superhero
🦸
just your average ordinary everyday superhero
  • 🇪🇺 European Union
  • 05:34 (UTC +02:00)
Block or Report

Block or report stnolting

Block user

Prevent this user from interacting with your repositories and sending you notifications. Learn more about blocking users.

You must be logged in to block users.

Please don't include any personal information such as legal names or email addresses. Maximum 100 characters, markdown supported. This note will be visible to only you.
Report abuse

Contact GitHub support about this user’s behavior. Learn more about reporting abuse.

Report abuse

Pinned

  1. neorv32 neorv32 Public

    🚀 A tiny, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.

    C 1.4k 200

  2. neoTRNG neoTRNG Public

    🎲 A Tiny and Platform-Independent True Random Number Generator for any FPGA (and ASIC).

    VHDL 153 15

  3. neorv32-verilog neorv32-verilog Public template

    ♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.

    Verilog 39 9

  4. neorv32-setups neorv32-setups Public

    📁 NEORV32 projects and exemplary setups for various FPGAs, boards and (open-source) toolchains.

    VHDL 52 15

  5. neorv32-riscof neorv32-riscof Public template

    ✔️Port of RISCOF to check the NEORV32 for RISC-V ISA compatibility.

    Python 24 5

  6. riscv-gcc-prebuilt riscv-gcc-prebuilt Public

    📦 Prebuilt RISC-V GCC toolchains for x64 Linux.

    Shell 75 8