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@darklife

Darklife

Research Foundation

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  1. darkriscv darkriscv Public

    opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

    Verilog 1.9k 270

Repositories

Showing 3 of 3 repositories
  • darkriscv Public

    opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

    Verilog 1,900 BSD-3-Clause 270 8 1 Updated Apr 18, 2024
  • darkdocs Public

    Darklife related documents

    0 BSD-3-Clause 0 0 0 Updated Aug 6, 2023
  • udarkrisc Public

    u[Dark]RISC -- "micro-darkrisc" -- an early 16-bit micro-RISC processor defined before DarkRISCV

    Verilog 11 BSD-3-Clause 2 0 0 Updated Jul 25, 2023

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