Creating this repo to document the learnings from the workshop Advanced Physical Design using OpenLANE/SKY130 conducted by VSD
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Updated
Aug 7, 2022
Creating this repo to document the learnings from the workshop Advanced Physical Design using OpenLANE/SKY130 conducted by VSD
This is part of EC383 - Mini Project in VLSI Design.
Advanced Physical Design Using OpenLANE/SKY130 course notes by Ojasvi Shah
This repository offers a compact design verification flow using OpenLANE. Scripts cover synthesis correctness, functional and power verification, DRC/LVS, timing analysis, and reliability checks. Contributions are welcome.
CLEAR is an Open Source FPGA ASIC delivered to you on its development board and its open source software development tools and all the ASIC design tools used to create it.
This is my openlane repository in which we perform synthesis of our design/module.
This repository is dedicated to VLSI ASIC Design Flow using open-source tools! Here, we embark on a journey that starts with specifications, RTL DV, Synthesis, Physical Design, Signoff and Finally Tape-It-Out
Picorv32-IM with exact and approximate SIMD multiplication extensions. The SIMD modules can be accessed with custom RISC-V Instruction to perform dual/quad 8-bit multiplications.
This project give overview of RTL to GDSII of universal shift register using OpenLane and Skywater130 PDK. OpenLane is an automated open-source EDA tool which gives RTL to GDSII flow.
Report of the contents learned in the 5-day workshop by VSD regarding the open-source EDA tools in the VLSI industry
Gate-level visualization generator for SKY130-based chip designs.
This repository documents my work on Advanced Physical Design Using OpenLANE/Sky130. The objective of this project was to implement an opensource RTL2GDS flow using OpenLANE and opensource PDK provided by Google/SkyWater130
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