The purpose of this project is to produce a clean GDS (Graphic Design System) Final Layout with all details that are used to print photomasks used in the fabrication of a behavioral RTL (Register-Transfer Level) of an 8-bit Priority Encoder, using SkyWater 130 nm PDK (Process Design Kit).
- Introduction
- Design Overview
- IP specs Provided
- Verilog behavioral design
- Pre-layout
- OpenLane
- Synthesis
- Floorplanning
- Placement
- Routing
- Layout vs Schematic
- Final Layout
- Post-layout
- Steps to reproduce and explore the design
- Key points to Remember
- Area of improvement
- References
- Acknowledgement
- Author
A Priority encoder is a combinational circuit which converts multiple bit-input signal to a encoded output signal in such a way that the output signal reassembles complete information which is fed at the input of the encoder. The encoder consists of ‘2n’ bits of input lines and ‘n’ bits output lines. The circuit of an encoder is based on the operation of Boolean expressions.
8-bit to 3-bit priority encoder is an encoder that consists of 8 input lines and 3 output lines. It can also be called an Octal to a binary encoder. Each input line has a base value of 8 (octal) and each output has a base value of 2 (binary).
Yosys synthesis
OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen, Fault and custom methodology scripts for design exploration and optimization. For more information check here
- Synthesis
yosys- Performs RTL synthesisabc- Performs technology mappingOpenSTA- Performs static timing analysis on the resulting netlist to generate timing reports
- Floorplan and PDN
init_fp- Defines the core area for the macro as well as the rows (used for placement) and the tracks (used for routing)ioplacer- Places the macro input and output portspdn- Generates the power distribution networktapcell- Inserts welltap and decap cells in the floorplan
- Placement
RePLace- Performs global placementResizer- Performs optional optimizations on the designOpenDP- Perfroms detailed placement to legalize the globally placed components
- CTS
TritonCTS- Synthesizes the clock distribution network (the clock tree)
- Routing
FastRoute- Performs global routing to generate a guide file for the detailed routerCU-GR- Another option for performing global routing.TritonRoute- Performs detailed routingSPEF-Extractor- Performs SPEF extraction
- GDSII Generation
Magic- Streams out the final GDSII layout file from the routed defKlayout- Streams out the final GDSII layout file from the routed def as a back-up
- Checks
Magic- Performs DRC Checks & Antenna ChecksKlayout- Performs DRC ChecksNetgen- Performs LVS ChecksCVC- Performs Circuit Validity Checks
- Preferred Ubuntu OS)
- Docker 19.03.12+
- GNU Make
- Python 3.6+ with PIP
- Click, Pyyaml:
pip3 install pyyaml click
$ sudo apt install -y git
$ git clone https://github.com/The-OpenROAD-Project/OpenLane.git
$ cd OpenLane/
$ make openlane
$ make pdk
$ make test # This a ~5 minute test that verifies that the flow and the pdk were properly installed
For detailed installation process, check here
make mount
- Note
- Default PDK_ROOT is $(pwd)/pdks. If you have installed the PDK at a different location, run the following before
make mount: - Default IMAGE_NAME is efabless/openlane:current. If you want to use a different version, run the following before
make mount:
- Default PDK_ROOT is $(pwd)/pdks. If you have installed the PDK at a different location, run the following before
The following is roughly what happens under the hood when you run make mount + the required exports:
export PDK_ROOT=<absolute path to where skywater-pdk and open_pdks will reside>
export IMAGE_NAME=<docker image name>
docker run -it -v $(pwd):/openLANE_flow -v $PDK_ROOT:$PDK_ROOT -e PDK_ROOT=$PDK_ROOT -u $(id -u $USER):$(id -g $USER) $IMAGE_NAME
You can use the following example to check the overall setup:
./flow.tcl -design spm
To run openlane in interactive mode
./flow.tcl -interactive
Terminal snap (To perform pre-layout simulation)
GTKWave output waveform
Synthesis reports
- Printing statistics.
=== dvsd_pe ===
Number of wires: 40
Number of wire bits: 51
Number of public wires: 5
Number of public wire bits: 14
Number of memories: 0
Number of memory bits: 0
Number of processes: 0
Number of cells: 42
$_ANDNOT_ 14
$_AND_ 1
$_DLATCH_P_ 3
$_NAND_ 3
$_NOR_ 3
$_ORNOT_ 6
$_OR_ 12
- Printing statistics.
=== dvsd_pe ===
Number of wires: 18
Number of wire bits: 27
Number of public wires: 5
Number of public wire bits: 14
Number of memories: 0
Number of memory bits: 0
Number of processes: 0
Number of cells: 18
sky130_fd_sc_hd__a21oi_2 1
sky130_fd_sc_hd__a311o_2 1
sky130_fd_sc_hd__a31o_2 1
sky130_fd_sc_hd__and3_2 1
sky130_fd_sc_hd__and4_2 1
sky130_fd_sc_hd__buf_1 1
sky130_fd_sc_hd__dlxtp_1 3
sky130_fd_sc_hd__inv_2 6
sky130_fd_sc_hd__o221ai_2 1
sky130_fd_sc_hd__or2_2 1
sky130_fd_sc_hd__or4_2 1
Chip area for module '\dvsd_pe': 147.641600
- Yosys synthesis strategies
# User config
set ::env(DESIGN_NAME) dvsd_pe
# Change if needed
set ::env(VERILOG_FILES) [glob $::env(DESIGN_DIR)/src/*.v]
# turn off clock
set ::env(CLOCK_TREE_SYNTH) 0
set ::env(CLOCK_PORT) ""
set ::env(PL_SKIP_INITIAL_PLACEMENT) 1
set ::env(PL_RANDOM_GLB_PLACEMENT) 0
set ::env(FP_SIZING) absolute
set ::env(DIE_AREA) "0 0 50 50"
set ::env(PL_TARGET_DENSITY) 0.75
set ::env(FP_HORIZONTAL_HALO) 6
set ::env(FP_VERTICAL_HALO) $::env(FP_HORIZONTAL_HALO)
set filename $::env(DESIGN_DIR)/$::env(PDK)_$::env(STD_CELL_LIBRARY)_config.tcl
if { [file exists $filename] == 1} {
source $filename
}
- Placement Analysis
total displacement 0.0 u
average displacement 0.0 u
max displacement 0.0 u
original HPWL 575.4 u
legalized HPWL 605.9 u
delta HPWL 5 %
- Routing resources analysis
Routing Original Derated Resource
Layer Direction Resources Resources Reduction (%)
---------------------------------------------------------------
li1 Vertical 735 622 15.37%
met1 Horizontal 980 746 23.88%
met2 Vertical 735 642 12.65%
met3 Horizontal 490 426 13.06%
met4 Vertical 294 250 14.97%
met5 Horizontal 98 78 20.41%
---------------------------------------------------------------
- Final congestion report
Layer Resource Demand Usage (%) Max H / Max V / Total Overflow
---------------------------------------------------------------------------------------
li1 622 40 6.43% 0 / 0 / 0
met1 746 33 4.42% 0 / 0 / 0
met2 642 0 0.00% 0 / 0 / 0
met3 426 0 0.00% 0 / 0 / 0
met4 250 0 0.00% 0 / 0 / 0
met5 78 0 0.00% 0 / 0 / 0
---------------------------------------------------------------------------------------
Total 2764 73 2.64% 0 / 0 / 0
- Routing resurces analysis
Routing Original Derated Resource
Layer Direction Resources Resources Reduction (%)
---------------------------------------------------------------
li1 Vertical 735 100 86.39%
met1 Horizontal 980 746 23.88%
met2 Vertical 735 642 12.65%
met3 Horizontal 490 426 13.06%
met4 Vertical 294 250 14.97%
met5 Horizontal 98 78 20.41%
---------------------------------------------------------------
- Final congestion report
Layer Resource Demand Usage (%) Max H / Max V / Total Overflow
---------------------------------------------------------------------------------------
li1 100 1 1.00% 0 / 0 / 0
met1 746 34 4.56% 0 / 0 / 0
met2 642 39 6.07% 0 / 0 / 0
met3 426 0 0.00% 0 / 0 / 0
met4 250 0 0.00% 0 / 0 / 0
met5 78 0 0.00% 0 / 0 / 0
---------------------------------------------------------------------------------------
Total 2242 74 3.30% 0 / 0 / 0
- Complete detail routing
Total wire length = 563 um.
Total wire length on LAYER li1 = 0 um.
Total wire length on LAYER met1 = 253 um.
Total wire length on LAYER met2 = 290 um.
Total wire length on LAYER met3 = 20 um.
Total wire length on LAYER met4 = 0 um.
Total wire length on LAYER met5 = 0 um.
Total number of vias = 182.
Up-via summary (total 182):.
----------------------
FR_MASTERSLICE 0
li1 89
met1 89
met2 4
met3 0
met4 0
----------------------
182
Run Directory: /openLANE_flow/designs/dvsd_pe/runs/run
----------------------------------------
Magic DRC Summary:
Source: /openLANE_flow/designs/dvsd_pe/runs/run3/reports/magic//31-magic.drc
Total Magic DRC violations is 0
----------------------------------------
LVS Summary:
Source: /openLANE_flow/designs/dvsd_pe/runs/run3/results/lvs/dvsd_pe.lvs_parsed.lef.log
LVS reports no net, device, pin, or property mismatches.
Total errors = 0
----------------------------------------
Antenna Summary:
Source: /openLANE_flow/designs/dvsd_pe/runs/run3/reports/routing//33-antenna.rpt
Number of pins violated: 0
Number of nets violated: 0
[INFO]: check full report here: /openLANE_flow/designs/dvsd_pe/runs/run3/reports/final_summary_report.csv
[INFO]: Saving Runtime Environment
[SUCCESS]: Flow Completed Without Fatal Errors.
- Subcircuit summary
Circuit 1: dvsd_pe |Circuit 2: dvsd_pe
-------------------------------------------|-------------------------------------------
sky130_fd_sc_hd__decap_12 (1) |sky130_fd_sc_hd__decap_12 (1)
sky130_fd_sc_hd__decap_8 (1) |sky130_fd_sc_hd__decap_8 (1)
sky130_fd_sc_hd__fill_2 (1) |sky130_fd_sc_hd__fill_2 (1)
sky130_fd_sc_hd__decap_4 (1) |sky130_fd_sc_hd__decap_4 (1)
sky130_fd_sc_hd__decap_6 (1) |sky130_fd_sc_hd__decap_6 (1)
sky130_fd_sc_hd__fill_1 (1) |sky130_fd_sc_hd__fill_1 (1)
sky130_fd_sc_hd__clkbuf_2 (5) |sky130_fd_sc_hd__clkbuf_2 (5)
sky130_fd_sc_hd__dlxtp_1 (3) |sky130_fd_sc_hd__dlxtp_1 (3)
sky130_fd_sc_hd__inv_2 (6) |sky130_fd_sc_hd__inv_2 (6)
sky130_fd_sc_hd__decap_3 (1) |sky130_fd_sc_hd__decap_3 (1)
sky130_fd_sc_hd__a41o_1 (1) |sky130_fd_sc_hd__a41o_1 (1)
sky130_fd_sc_hd__and4_1 (1) |sky130_fd_sc_hd__and4_1 (1)
sky130_fd_sc_hd__nor2_1 (1) |sky130_fd_sc_hd__nor2_1 (1)
sky130_fd_sc_hd__a311o_1 (1) |sky130_fd_sc_hd__a311o_1 (1)
sky130_fd_sc_hd__or2_1 (1) |sky130_fd_sc_hd__or2_1 (1)
sky130_fd_sc_hd__buf_1 (7) |sky130_fd_sc_hd__buf_1 (7)
sky130_fd_sc_hd__clkbuf_1 (3) |sky130_fd_sc_hd__clkbuf_1 (3)
sky130_fd_sc_hd__tapvpwrvgnd_1 (1) |sky130_fd_sc_hd__tapvpwrvgnd_1 (1)
sky130_fd_sc_hd__o221ai_1 (1) |sky130_fd_sc_hd__o221ai_1 (1)
sky130_fd_sc_hd__a21oi_1 (1) |sky130_fd_sc_hd__a21oi_1 (1)
sky130_fd_sc_hd__or4_1 (1) |sky130_fd_sc_hd__or4_1 (1)
Number of devices: 40 |Number of devices: 40
Number of nets: 43 |Number of nets: 43
---------------------------------------------------------------------------------------
Circuits match uniquely.
Netlists match uniquely.
- Subcircuits pins
Circuit 1: dvsd_pe |Circuit 2: dvsd_pe
-------------------------------------------|-------------------------------------------
in[0] |in[0]
in[1] |in[1]
in[2] |in[2]
in[5] |in[5]
in[4] |in[4]
in[3] |in[3]
en |en
in[6] |in[6]
in[7] |in[7]
eno |eno
out[2] |out[2]
out[0] |out[0]
out[1] |out[1]
gs |gs
VGND |VGND
VPWR |VPWR
---------------------------------------------------------------------------------------
- lef layout
- Magic layout
- tkcon window
- Klayout GDS
- Klayout XOR check
Terminal snap (To perform post-layout simulation)
GTKWave output waveform
- Clone the project using following command
$ git clone https://github.com/Khalique13/dvsd_pe_sky130.git
- To explore Pre-layout simulation
$ cd pre_layout_simulaion/
$ gtkwave dvsd_pe.vcd
- To explore floorplan
$ cd floorplan/
$ magic -T sky130A.tech lef read merged.lef def read dvsd_pe.floorplan.def &
- To explore placement
$ cd placement/
$ magic -T sky130A.tech lef read merged.lef def read dvsd_pe.placement.def &
- To explore final layout
# to view Magic layout
$ cd layout-magic/
$ magic dvsd_pe.mag
# to view GDS view using Klayout
$ cd layout-klayout/
$ klayout dvsd_pe.gds
- To explore Post-layout (Gate Level Simulation)
$ cd post_layout_simulation/
$ gtkwave gls.vcd
- Complete details, logs and results can be found under this folder.
dvsd_pe
├── config.tcl
├── runs
│ ├── run
│ │ ├── config.tcl
│ │ ├── logs
│ │ │ ├── cts
│ │ │ ├── cvc
│ │ │ ├── floorplan
│ │ │ ├── klayout
│ │ │ ├── magic
│ │ │ ├── placement
│ │ │ ├── routing
│ │ │ └── synthesis
│ │ ├── reports
│ │ │ ├── cts
│ │ │ ├── cvc
│ │ │ ├── floorplan
│ │ │ ├── klayout
│ │ │ ├── magic
│ │ │ ├── placement
│ │ │ ├── routing
│ │ │ └── synthesis
│ │ ├── results
│ │ │ ├── cts
│ │ │ ├── cvc
│ │ │ ├── floorplan
│ │ │ ├── klayout
│ │ │ ├── magic
│ │ │ ├── placement
│ │ │ ├── routing
│ │ │ └── synthesis
│ │ └── tmp
│ │ ├── cts
│ │ ├── cvc
│ │ ├── floorplan
│ │ ├── klayout
│ │ ├── magic
│ │ ├── placement
│ │ ├── routing
│ │ └── synthesis
- Keep the top module name and design name always, else errors would come in the design.
- This project is a Combinaional block hence there is no clock, static time analysis is being skiped.
- Improvement in the design with more complex design and parameters.
- GitLab/OpenLane workshop
- The OpenROAD Project/OpenLane
- Ahmed Ghazy and Mohamed Shalan, "OpenLane: The Open-Source Digital ASIC Implementation Flow", Article No.21, Workshop on Open-Source EDA Technology (WOSET), 2020. Paper
Kunal Ghosh, Founder, VSD Corp. Pvt. Ltd
- Contact: kunalpghosh@gmail.com
- Contact: gjkhalique@gmail.com