OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.
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Updated
Apr 28, 2024 - Python
OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.
Deep learning toolkit-enabled VLSI placement
IP Core Library - Published and maintained by the Chair for VLSI Design, Diagnostics and Architecture, Faculty of Computer Science, Technische Universität Dresden, Germany
A High-performance Timing Analysis Tool for VLSI Systems
A modern and open-source cross-platform software for chips reverse engineering.
Open source software for chip reverse engineering.
Gain an understanding of the fundamentals of Very Large-Scale Integration (VLSI), including how the theories and concepts can be applied in the design of simple logic circuits and in the physical implementation of a simplified microprocessor
Standard Cell Library based Memory Compiler using FF/Latch cells
Create fast and efficient standard cell based adders, multipliers and multiply-adders.
GDSII File Parsing, IC Layout Analysis, and Parameter Extraction
ACT hardware description language and core tools.
A browser-based SPICE circuit simulator
Xplace 2.0: An Extremely Fast, Extensible and Deterministic Placement Framework with Detailed-Routability Optimization
FAN (fan-out-oriented) ATPG (Automatic Test Pattern Generation) and Fault Simulation command line tool
EDAV: Open-Source EDA Viewer; render design LEF/DEF files in your browser!
VLSI EDA Global Router
Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)
A Fast C++ Header-only Parser for Standard Parasitic Exchange Format (SPEF).
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