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chip-design

Here are 9 public repositories matching this topic...

JackonYang / paper-reading

比做算法的懂工程落地，比做工程的懂算法模型。

arxiv computer-architecture tvm mlir chip-design llm

Updated Mar 31, 2024
Jupyter Notebook

patrickschulz / openPCells

Parametric layout generator for digital, analog and mixed-signal integrated circuits

lua analog cadence integrated-circuits pcells parametric-cells chip-design layout-automation

Updated May 10, 2024
C

mabrains / sky130_klayout_pdk

Skywater 130nm Klayout Device Generators PDK

custom-layout pdk pcells skywaters analog-layout chip-design

Updated Jan 7, 2023
Python

flaport / condalayout

Conda + KLayout

design electronics layout conda eda chip klayout photonics epda chip-design

Updated Aug 21, 2022
Dockerfile

arhamhashmi01 / rv32i-pipeline-processor

This repository contain the implementaton of RV32I 5-Stage-Pipeline-Processor based on RISC-V ISA and designed on Verilog

vhdl verilog microprocessor hardware-designs computer-architecture gtkwave vlsi pipeline-processor risc-v rv32i verilator asic-design chip-design 5-stage-pipelined-processor rv32i-processor

Updated Mar 22, 2024
Verilog

XS-MLVP / xcomm

xspcomm encapsulates the DPI-based digital circuit and provides various high-level language operation interfaces.

verification multilanguage chip-design

Updated May 10, 2024
C++

ojasvi-shah / Advanced-Physical-Design-Using-OpenLANE--Ojasvi-Shah

Advanced Physical Design Using OpenLANE/SKY130 course notes by Ojasvi Shah

virtualbox riscv vlsi openlane chip-design

Updated Mar 30, 2024

electricalgorithm / introduction-to-VHDL-projects

VHDL Projects that I've created during the course Programmable Logic Devices in West Pomeranian University of Technology in Szczecin.

mux comparator seven-segment traffic-light-controller chip-design digtial-design adder-circuit line-buffer ring-counter four-digit-seven-segment-driver

Updated May 30, 2022
VHDL

Noamv7 / Matrix-Multiplication-Using-Systolic-Arrays-Chip-Design-and-Verification

This project is focused on the design and verification of digital logic circuits, particularly targeting chip design using Verilog, SystemVerilog, and SVA. The main objectives included designing modules compliant with industry standards such as APB (Advanced Peripheral Bus), memory systems, and systolic matrix multiplication.

verification matrix-multiplication verilog systemverilog questasim logic-design sva systolic-arrays amba-apb functional-coverage chip-design

Updated Apr 8, 2024
Verilog

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