gtkwave
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Laboratory Mini Project for the Course - Digital Design and Computer Organization (UE22CS251A)
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Dec 22, 2023 - Verilog
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Jan 9, 2021 - SystemVerilog
Implementación del procesador monociclo RISC-V en System Verilog.
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May 6, 2024 - SystemVerilog
Course Project - Advanced Computer Architecture - Autumn Semester 2022 - Indian Institute of Technology Bombay
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Dec 13, 2022 - VHDL
A simple up-down counter project made using icarus verilog as a part of the Digital Design and Computer Organization course (UE19CS207) at PES University.
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Dec 6, 2020 - Verilog
Pre and Post Synthesis Simulation of a Design VSDMemSOC
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May 5, 2024 - Verilog
Simple MIPS 16-bit CPU implemented in VHDL with an assembler in python
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Apr 30, 2024 - VHDL
VHDL fpga exersises with Free/FOSS/Libre tools
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Nov 19, 2023 - VHDL
This repository contains an extensive learning journey of SystemVerilog, exercises and projects to enhance the understanding and proficiency in the hardware description language
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Apr 11, 2024 - SystemVerilog
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