Discover and create logic circuits

Flip flop setup, hold & metastability explorer tool

Materials for the Computer Science course, Digital Design (Logic Circuits)

FuzzyNSGA-II-Algorithm (Fuzzy adaptive optimisation method)

Implementaciones para diseño de sistemas digitales, comenzando por Flip Flops, registros, autómatas (Máquinas de Moore y Máquinas de Mealy), memorias ROM y sensores de presencia, utilizando para cada uno de estos, distintos contadores (anillo, década, etc).

An eurorack logic module with several logic functions and a clock divider mode. Build around an arduino nano. So could be reprogrammed.

💻 Repositório para Disciplina EEL5105 - Circuitos e Técnicas Digitais - UFSC

this source is Commercial bcd counter that built with Jk flip-flop in verilog

Latch and Flip Flop Analysis Using Hspice

Download my Redstone World: https://www.planetminecraft.com/project/redstone-circuits-6024948/

This GitHub repository contains coursework projects related to computer systems design. It includes various assignments and projects that cover topics such as digital logic design, computer architecture, and hardware description languages.

This MPLAB X Melody code example shows how to make an LED blink using the Configurable Custom Logic (CCL) found in the AVR® DB. The CCL is configured as a toggling J-K flip-flop. The toggling is a result of a timer event.

Compilation of Verilog behavioral models and test benches for the four types of flip-flops (SR, JK, D, and T)

porject from designing with VHDL course. Includes, FSM (finite state machine), next state logic,seven-segment-display-decode, full adder, flip flops, D_flip-flops, ripple carry adder, full adder, half adder, delay propagation

Logic Circuits using Logisim

Testers for some non elementary integrated circuits: Adder 74283, D Flip-Flop 74174 & Counter 74193 written to be run from PSoC 4

CSE-2112 Digital Syatem Design LAb

Playing with ⚡ logic gates to make corresponding ✔ decision making circuits solving 🔌 electronic challenges at hand 🚦

A simple up-down counter project made using icarus verilog as a part of the Digital Design and Computer Organization course (UE19CS207) at PES University.