This is a sequence generator for even numbers (0, 2, 4, 6, ...) which resets to 0 after every cycle. Done as a project for the subject 'Digital Design and Computer Organisation - Laboratory' (UE19CS207).
All codes in this repository have been implemented in Verilog. All output waveforms have been displayed using GTKWave.
- Algorithmic Implementation - no circuitry is used in this code
- Implementation of Circuit - circuit components are used in this code