asic
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Digital Signature Service : creation, extension and validation of advanced electronic signatures
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May 13, 2024 - Java
OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.
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May 14, 2024 - Python
VUnit is a unit testing framework for VHDL/SystemVerilog
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May 21, 2024 - VHDL
AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
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May 8, 2024 - SystemVerilog
RISC-V CPU Core (RV32IM)
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Sep 18, 2021 - Verilog
🖥️ A tiny, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.
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May 22, 2024 - VHDL
Haskell to VHDL/Verilog/SystemVerilog compiler
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May 21, 2024 - Haskell
Cryptocurrency ASIC mining hardware monitor using a simple web interface
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May 1, 2023 - Python
32-bit Superscalar RISC-V CPU
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Sep 18, 2021 - Verilog
collection of works aiming at reducing model sizes or the ASIC/FPGA accelerator for machine learning
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Feb 3, 2024
Verilog implementation of the symmetric block cipher AES (Advanced Encryption Standard) as specified in NIST FIPS 197. This implementation supports 128 and 256 bit keys.
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Feb 8, 2023 - Verilog
Embedded Scalable Platforms: Heterogeneous SoC architecture and IP integration made easy
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May 17, 2024 - C
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