Skip to content

Pull requests: VUnit/vunit

New pull request New
52 Open 376 Closed
52 Open 376 Closed
Author
Filter by author
Label
Filter by label
Use alt + click/return to exclude labels
or ⇧ + click/return for logical OR
Projects
Filter by project
Milestones
Filter by milestone
Reviews
Filter by reviews
No reviews Review required Approved review Changes requested
Assignee
Filter by who’s assigned
Sort
Sort by
Newest Oldest Most commented Least commented Recently updated Least recently updated Best match
Most reactions
👍 👎 😄 🎉 😕 ❤️ 🚀 👀

Pull requests list

Support arbitrary waveform viewer
Enhancement Tool: GtkWave Tool: Surfer
#1002 opened Mar 12, 2024 by oscargus • Draft
1
2
Remove redundant directory from Riviera-PRO dataset path
Enhancement Tool: RivieraPro
#995 opened Mar 6, 2024 by por3bski Loading… v5.0.0
1
Fix regex for VHDL component instantiations
#990 opened Feb 29, 2024 by javValverde Loading… v5.0.0
2
VHDL-embedded Python code
#986 opened Jan 16, 2024 by LarsAsplund • Draft
14
fix dependency for vhdl instances inside (Sysytem) verilog modules
#979 opened Nov 24, 2023 by roynil Loading…
sim_if/modelsim: use vmap to find modelsim.ini
#975 opened Nov 7, 2023 by bjornfor Loading…
Add Block Design support for simulation
#962 opened Oct 19, 2023 by SzymonHitachi Loading…
1
12
Added/Fixed Typing for all files in vunit.ui package
Enhancement
#961 opened Sep 28, 2023 by g0t00 Loading… v5.0.0
10
Fix issues when trying to parameterize Verilog modules
#945 opened Jul 12, 2023 by piotrva Loading…
1
7
Move project metadata to pyproject.toml
Enhancement
#942 opened Jul 7, 2023 by lavovaLampa Loading… v5.1.0
7
Add type hints to 'parsing/' package
Enhancement Parsing
#939 opened May 27, 2023 by lavovaLampa Loading…
5
Unaligned addresses with axi_read_slave
#936 opened May 16, 2023 by crdavis12 Loading…
2
Parity bit in the uart VCs Enhancement Verification Components
#906 opened Feb 26, 2023 by nicdes Loading… v5.1.0
Improved changelog to be automatically managed by towncrier CI Docs Enhancement
#885 opened Jan 6, 2023 by GlenNicholls Loading…
3 of 6 tasks
v5.1.0
17
Fix some Vivado issues (SystemVerilog support, space in file name, environment variable)
Docs Enhancement Simulator support
#871 opened Nov 7, 2022 by oscargus Loading… v5.1.0
3
30
Working Xcelium + Indago support with single command commpilation plus a basic rerun script for Xcelium
#866 opened Nov 1, 2022 by Hardolaf Loading…
109
Add a specific menu for VUnit in ModelSim GUI Enhancement Tool: Questa
#844 opened Jun 23, 2022 by std-max Loading…
1
5
proposal for vhdl_parser to fix the issue #808 Enhancement Parsing
#839 opened Jun 1, 2022 by asicnet Loading… v5.1.0
2
Improving regexs that scan attributes Enhancement
#836 opened May 31, 2022 by std-max Loading… v5.1.0
1
5
Detect dual test case run Builtins Enhancement
#824 opened May 10, 2022 by std-max Loading… v5.1.0
1
5
Rework codec
#822 opened Apr 28, 2022 by dalex78 Loading…
43
Peek functionality
#814 opened Apr 17, 2022 by dalex78 Loading…
12
Add feature to select simulator programatically Enhancement Simulator support
#805 opened Mar 6, 2022 by nfrancque Loading… v5.1.0
5
Add configuration support
Enhancement ThirdParty: OSVVM Related to OSVVM and/or OSVVMLibraries.
#785 opened Jan 1, 2022 by LarsAsplund Loading… v5.1.0
7
Support hierarchical library mapping in ModelSim Enhancement Tool: Questa
#775 opened Oct 30, 2021 by ThomasWismer Loading… v5.1.0
12
ProTip! Add no:assignee to see everything that’s not assigned.