Discussions

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  how to update config.json when my design with two clock input with different frequence?

  TonyHo722 asked Oct 24, 2023 in Q&A · Answered

  

  

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  Using a slice of a multi-bit port as clock name

  scorbetta asked Mar 19, 2024 in Q&A · Answered

  

  

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  Constraining a synchronizer

  scorbetta asked Mar 29, 2024 in Q&A · Unanswered

  

  

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  Error pdn-0175 (pitch is too small)

  krissjarvis asked May 2, 2023 in Q&A · Unanswered

  

  

  

  

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  Installation problem: can't find flow.tcl after run "make test"

  doctor-TZ asked Jan 28, 2024 in Q&A · Unanswered

  

  

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  Custom PDK

  ashkanr65 asked Dec 13, 2023 in General · Unanswered

  

  

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  Magic DRC Errors

  tdtu1002 asked Nov 18, 2023 in Q&A · Unanswered

  

  

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  ORFS Check antenna: Command terminated by signal 6

  marcopoles asked Oct 19, 2023 in Q&A · Unanswered

  

  

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  regarding formal verification of design in openlane

  Vinayakamk asked Oct 9, 2023 in Ideas · Closed · Unanswered

  

  

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  ERROR: Re-definition of module `\para_ser_01'!

  yslim2002 asked Sep 18, 2023 in Q&A · Unanswered

  

  

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  How to resolve the linter error

  vijayank88 asked Sep 2, 2023 in General · Closed · Answered

  

  

  

  

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  Max Fanout

  AayushiRV asked Aug 17, 2023 in General · Unanswered

  

  

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  IO pads generation

  akhilesh911 asked Aug 11, 2023 in General · Unanswered

  

  

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  ECO flow

  AayushiRV asked Aug 8, 2023 in General · Closed · Unanswered

  

  

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  OpenLane quit at synthesis stage but no apparent error

  heliboy2003 asked Aug 7, 2023 in Q&A · Closed · Unanswered

  

  

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  SPEF extraction in interactive mode

  akhilesh911 asked Aug 1, 2023 in Q&A · Unanswered

  

  

  

  

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  Slew margin in openlane flow

  akhilesh911 asked Jul 28, 2023 in Q&A · Closed · Answered

  

  

  

  

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  How to run ci moved designs list

  vijayank88 asked Jul 17, 2023 in General · Closed · Answered

  

  

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  Dockerized Openlane - yosis systemverilog support

  Andrea-Spitale asked Jul 16, 2023 in Q&A · Unanswered

  

  

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  Debugging OpenLane Seg Fault

  ShvetankPrakash asked Jul 14, 2023 in General · Unanswered

  

  

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  Error IR Drop in caravel_user_project with an OpenFPGA

  CristopherA96 asked Jun 19, 2023 in Q&A · Unanswered

  

  

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  Error with verilator lint check process in latest Openlane's version

  CristopherA96 asked May 3, 2023 in Q&A · Unanswered

  

  

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  Errors working witn OpenFPGA files in latest Version of OpenLane

  CristopherA96 asked May 3, 2023 in Q&A · Unanswered

  

  

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  Where is pdk folder?

  eusanchez asked Apr 20, 2023 in Q&A · Closed · Unanswered

  

  

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  sta.tcl script, trying to show all scripts in max and min reports

  eusanchez asked Apr 4, 2023 in Q&A · Unanswered

  

  

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