Pinned

1. pulp pulp Public

   This is the top-level project for the PULP Platform. It instantiates a PULP open-source system with a PULP SoC (microcontroller) domain accelerated by a PULP cluster with 8 cores.

   SystemVerilog 416 112

2. pulpissimo pulpissimo Public

   This is the top-level project for the PULPissimo Platform. It instantiates a PULPissimo open-source system with a PULP SoC domain, but no cluster.

   SystemVerilog 349 155

3. cheshire cheshire Public

   A minimal Linux-capable 64-bit RISC-V SoC built around CVA6

   SystemVerilog 105 28

4. snitch_cluster snitch_cluster Public

   An energy-efficient RISC-V floating-point compute cluster.

   SystemVerilog 26 29

5. axi axi Public

   AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication

   SystemVerilog 928 239

6. ara ara Public

   The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 core

   C 304 106