Sublime Text snippets for UVM

cmake trial for rtl development

Basic Stopwatch Design using Terasic DE-10 Standard FPGA

Here you'll find the game "Donkey Kong" written 100% in SysVerilog. You'll need an FPGA card, a screen, a keyboard, and audio devices for the full functionality.

Extending the MIPS32 Single Cycle Processor Instruction Set.

A single SystemVerilog package with both classes of half as well as full adder is created and tested using the testbench

This project is focused on the design and verification of digital logic circuits, particularly targeting chip design using Verilog, SystemVerilog, and SVA. The main objectives included designing modules compliant with industry standards such as APB (Advanced Peripheral Bus), memory systems, and systolic matrix multiplication.

Contains Small projects on Verification Using System Verilog

Single-cycle single-core MIPS processor

Formal verification experiments

AXI4-Lite compatible Driver module for use with Verilator and other DPI-C compatible simulators.

Script de PowerShell para configurar rápidamente un entorno de desarrollo SystemVerilog, incluyendo la instalación de VS Code, extensiones relevantes y herramientas de compilación

A Pokemon-style RPG built for the Altera FPGA DE2-115 Development Board for ECE 385

A pipeline implementation of the MIPS processor

Screen Saver for linux system with a ball bouncing

My SystemVerilog Projects.

Example to test all UPduino GPIO outputs