This repository contains the Verilog code for a matrix multiplication design implemented using systolic arrays. The project is divided into two main parts: the Design Part and the Verification Part.
The Design Part focuses on the implementation of the matrix multiplication algorithm using systolic arrays. Various modules including the APB slave, memory, processing elements (PE), and the main matrix multiplication calculation module are implemented in Verilog. These modules interact to perform matrix multiplication efficiently.
The Verification Part aims to ensure the correctness and functionality of the matrix multiplication design through rigorous verification techniques. Simulation-based testing, functional checking, functional coverage analysis, and comparison with a Python-based golden model are conducted to validate the design under various conditions and inputs.
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Design Part:
- Verilog modules for APB slave, memory, processing elements, and matrix multiplication calculation.
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Verification Part:
- Header and package files containing system parameters and definitions.
- Testbench, tester, functional checker, and functional coverage modules for verification.
- Python-based golden model for comparison.
The matmul_interface.sv file defines the interface for communication between the design and the testbench. It includes signals for clock, reset, control, and data transmission.
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Design Part: Instantiate and interconnect the design modules according to system requirements. Ensure proper clocking and reset signals for correct functionality.
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Verification Part: Run simulation-based testing using the provided testbench and modules. Monitor functional behavior using the functional checker and analyze coverage metrics using the functional coverage module.
This project presents an efficient implementation of matrix multiplication using systolic arrays, accompanied by thorough verification to ensure accuracy and reliability. For further inquiries or assistance, please contact [insert contact information].