- design consists of VGA timing generator, image generator and VGA top
- parameterizable timing generator, default values correspond to VGA 640 x 480 @ 60 Hz Industry standard timing
- image generator generates a standard test frame
This is a short tabular description of the contents of each folder in the repo.
| Folder | Description |
|---|---|
| rtl/SystemVerilog | SV RTL implementation files |
| rtl/VHDL | VHDL RTL implementation files |
| cocotb_sim | Functional Verification with CoCoTB (Python-based) |
| verilator_sim | Functional Verification with Verilator (C++ based) |
| formal | Formal Verification using PSL properties and YoysHQ/sby |
This is the tree view of the strcture of the repo.
. ├── rtl │ ├── SystemVerilog │ │ └── SV files │ └── VHDL │ └── VHD files ├── cocotb_sim │ ├── Makefile │ └── python files ├── verilator_sim │ ├── Makefile │ └── verilator tb └── formal ├── Makefile └── PSL properties file, scripts