A eurorack-friendly audio frontend compatible with many FPGA boards.
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Updated
Apr 26, 2024 - SystemVerilog
A eurorack-friendly audio frontend compatible with many FPGA boards.
Python packages providing a library for Verification Stimulus and Coverage
Functional Coverage and Constrained Randomization Extensions for Cocotb
Limited python / cocotb interface to Xilinx/AMD Vivado simulator.
mirror of https://git.elphel.com/Elphel/vdt-plugin
Cosimulation for the Rapid Open Hardware Development (ROHD) framework with other simulators
Branch Predictor Optimization for BlackParrot
Library of hardware accelerators for popular cryptographic hash functions in SystemVerilog
Docker image for fpga development
This repository contains the Verilog HDL implementation of a Car Parking System running on an FPGA. The system is designed to manage car entry and exit through two sensors located at the entrance and exit of the car park. It allows registered users to enter the car park by entering their passwords and controls the traffic lights accordingly.
Example workflow project for VHDL development.
Design & Verification of IP Cores and ICs, Artificial Intelligence
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