Pinned

1. FPGA_Matrix_Timer_verilog FPGA_Matrix_Timer_verilog Public

   Design and implementation an embedded system using an FPGA to create a versatile timer with alarm functionality. The system utilises a multiplexed 7-segment display for time visualization, DIP swit…

   Verilog

2. 8-Bit-Even-up-Counter-SystemVerilog 8-Bit-Even-up-Counter-SystemVerilog Public

   Counter that counts even numbers is created using a chain of eight D flip-flops. An OOP-based test bench and a package is developed to verify the counter's functionality as a black box and compare …

   SystemVerilog 2

3. Diabetic-foot-monitoring-system Diabetic-foot-monitoring-system Public

   This is the code for the product that I made as a part of my internship. This project was undertaken with my teammates Sourabh and Tushar as a part of internship which was held between 3rd and 4th …

   Python 1

4. Counter_with_Parallel_load_SystemVerilog Counter_with_Parallel_load_SystemVerilog Public

   An 8-bit counter that counts from 0 to 255 when it is enabled and parallelly loaded. Structural approach is used here and treated as a black box and is verified using OOP based testbench.

   SystemVerilog

5. Travel_Guide_App Travel_Guide_App Public

   Developed during my time as an inturn at Electromotive. This app includes a display of several destination using a grid layout, and subsequent descriptive pages for each destination

   Java 1

6. 0_to_9999_BCD_Counter_Verilog 0_to_9999_BCD_Counter_Verilog Public

   A BCD counter that counts from 0 to 9999 is created and is verified on the multiplexed 7-segment display on the Spartan 6 FPGA.

   Verilog