Machine learning on FPGAs using HLS
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Updated
May 16, 2024 - C++
Machine learning on FPGAs using HLS
DaCe - Data Centric Parallel Programming
Course Project for CS577, Using keras2c to make machine learning model vivado synthesizable
A collection of extensions for Vitis and Intel FPGA OpenCL to improve developer quality of life.
Multi-Clock Dataflow Automation and Throughput Optimization in High-Level Synthesis
Implementation of the N^2-formulation of N-body simulation with Vivado HLS for SDAccel platforms.
This framework was part of the Diploma thesis titled "Architectures and Implementations of the Neural Network LeNet-5 in FPGAs". The main goal of this thesis was to create a LeNet-5 implementation in an FPGA development board, but also form a reusable framework/workflow which can be modified to model and develop other Neural Networks as well.
University of Pittsburgh ECE 1195
Course taken by Dr Chandan Karfa of Dept. of CSE, IIT Guwahati.
Reconfigurable Digital Systems HRY591-project.
running ANN on an FPGA
[FPGA 2021, Best Paper Award] An automated floorplanning and pipelining tool for Vivado HLS.
Here we are implementing Risc-V single cycle microprocessor on Basys3 (Artix-7) .We are testing with Fibonaccie Series and showing on 7 segment display..
MNIST accelerator using pynq-z2 and the binary qunatization
Accelerated Stencil Computation with Optimized Dataflow Architecture on FPGAs
An Optimal Microarchitecture for Stencil Computation Acceleration Based on Nonuniform Partitioning of Data Reuse Buffers on FPGAs
Real-time binocular stereo vision FPGA system with OV5640 cameras
FPGA acceleration of arbitrary precision floating point computations.
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