Image Processing Toolbox in Verilog using Basys3 FPGA
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Updated
Sep 19, 2023 - VHDL
Image Processing Toolbox in Verilog using Basys3 FPGA
A Single Cycle Risc-V 32 bit CPU
👻 Simple Undertale-like game on Basys3 FPGA written in Verilog
Demo of how to use https://github.com/openXC7 tools (yosys+nextpnr-xilinx) to implement the HW side of a custom SoC with RISC-V CPU & our special Video Controller in Basys3 Artix7-35T. Complemented with SW in the bare-metal 'C' they, together, make for this classic game. Except that it's now, in the standard BiH tradition, with a twist of our own.
Single Cycle 32 bit MIPS
This repository has basic examples in VHDL using Basys3 board.
Selected projects from "Applied Digital Logic Exercises using FPGAs", by Kurt Wick.
Digital clock implemented in vhdl for the Basys 3 Board from Digilent.
Logic Analyzer IP Core
Color Detection using Basys3 FPGA
This project aims to test how fast you can respond after seeing a visual stimulus or rather hand-eye coordination.
Digital Clock for the Basys 3 FPGA
Here we are implementing Risc-V single cycle microprocessor on Basys3 (Artix-7) .We are testing with Fibonaccie Series and showing on 7 segment display..
FPGA Audio Effect System project for Electronic Engineering course. This project spanned two semesters and was my final year project
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