RISC-V-Microprocessor-verilog-code-implementation-Artix-7-tested-with-Fibonacci-series-on-7seg

Here we are implementing Risc-V single cycle microprocessor on Basys3 (Artix-7) .We are testing with Fibonaccie Series and showing on 7 segment display.. Here we are using Vivado HLx software to generate bitstream for Basys3 kit and using Artix-7. I have also shared .xdc file for basys3.You have to customize .xdc file according to your requirement.

Name		Name	Last commit message	Last commit date
Latest commit History 4 Commits
.gitignore		.gitignore
ALU.v		ALU.v
ALUControl.v		ALUControl.v
Adder.v		Adder.v
Architecture Block diagram.jpg		Architecture Block diagram.jpg
DataMemory.v		DataMemory.v
ImmediateGeneration.v		ImmediateGeneration.v
Instructionmemory.v		Instructionmemory.v
LICENSE		LICENSE
MUX.v		MUX.v
MUX1.v		MUX1.v
PC Counter.v		PC Counter.v
README.md		README.md
Read Me.txt		Read Me.txt
Registerfile.v		Registerfile.v
add.v		add.v
architecture.v		architecture.v
basys3_xdc.xdc		basys3_xdc.xdc
maincontroller.v		maincontroller.v

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