All the projects and assignments done as part of VLSI course.
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Updated
Sep 23, 2020 - Verilog
All the projects and assignments done as part of VLSI course.
work done as part of VLSI Design practice course
Performed a comparative study of Parallel Prefix Adders using Verilog HDL on Zynq-7000 APSoC (PL) from XIlinx. Circuits are simulated, synthesized and implemented using Vivado Design Suite.
A repository for some modules I made while learning Verilog
An 4-bit multiplier is synthesized and simulated in Xilinx ISE using Verilog HDL. The multiplication is performed using Vedic Mathematics which is proved to consume less power and faster than conventional multipliers.
designed simple digital circuits using verilog
Digital System Design Lab Codes using Verilog
Useful VHDL scripts for hardware description.
Progetto di Elettronica Digitale AA 2022-2023
Parametrized Verilog implementation of different architectures of adder / subtractor circuits.
My VHDL Codes during EE214 (Digital Lab) Spring 2020-21
porject from designing with VHDL course. Includes, FSM (finite state machine), next state logic,seven-segment-display-decode, full adder, flip flops, D_flip-flops, ripple carry adder, full adder, half adder, delay propagation
A 4-bit ripple-carry adder-subtractor created in Logisim.
Skript zur Einführung in die Digitaltechnik
Computer Architecture - Practical Solution with Quartus - Sharif University of Technology
explore different implementations of adders and study their characteristics.
Add a description, image, and links to the ripple-carry-adder topic page so that developers can more easily learn about it.
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