GitHub - Ajay-Sai-Reddy/Vedic-Multiplier: An 4-bit multiplier is synthesized and simulated in Xilinx ISE using Verilog HDL. The multiplication is performed using Vedic Mathematics which is proved to consume less power and faster than conventional multipliers.

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An 4-bit multiplier is synthesized and simulated in Xilinx ISE using Verilog HDL. The multiplication is performed using Vedic Mathematics which is proved to consume less power and faster than conventional multipliers.

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Name		Name	Last commit message	Last commit date
Latest commit History 1 Commit
fourbit_adder.v		fourbit_adder.v
fourbit_multi.v		fourbit_multi.v
full_adder.v		full_adder.v
half_adder.v		half_adder.v
nrml_multiplier.v		nrml_multiplier.v
rca4.v		rca4.v
sixbit_adder.v		sixbit_adder.v
twobit_multi.v		twobit_multi.v