Name		Name	Last commit message	Last commit date
Latest commit History 15 Commits
magic		magic
verilog		verilog
.gitignore		.gitignore
README.md		README.md

Repository files navigation

VLSI

All the projects and assignments done as part of VLSI course.

About

All the projects and assignments done as part of VLSI course.

magic verilog vlsi wallace-tree-multiplier cmos vlsi-circuits recursive-doubling-cla ripple-carry-adder universal-shift-register

Report repository

Releases

No releases published

Packages

No packages published

Languages

Verilog 100.0%