Repository containing the code for implementing the classic game Pong on a Nexys A7 Digilent FPGA development board.
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Updated
Mar 1, 2024 - SystemVerilog
Repository containing the code for implementing the classic game Pong on a Nexys A7 Digilent FPGA development board.
IP Module For LTC2311 ADC
This repository contains different modules which execute arithmetic operations.
A slot machine created in System Verilog. It was built, simulated, synthesized, and implemented in Vivado, for use on the Xilinx Basys 3 board.
Школа инженера от DigitalDesign
Basic digital lock system for safes, employing logic gates 🔐
Took a module on Digital Design Fundamentals during my year 2 of my undergraduate studies of Electronic Circuits done using VHDL and Verilog, with a final project on FPGA Programmed Flappy Bird Gaming System using Sound and Light effects.
EDAV: Open-Source EDA Viewer; render design LEF/DEF files in your browser!
RTL Designs along with testbenches to verify them written in Verilog. Icarus Verilog an open source simulator was used for simulations.
FIFO buffer library. Written and verified in SystemVerilog. Can be synthetised in ASIC or FPGA.
5 stage pipelined RISC-V core with AXI3 bus protocol between the directly mapped cache and main memory.
RTL Design and Synthesis Workshop using Verilog with Sky130 Technology
A repo to store the coursework I do in college! 🎓
Very simple Cortex-M1 SoC design based on ARM DesignStart
Educational repo for storing my practice sessions with digital systems as well as solutions to online courses or university courses I take. These implementations are done in VHDL or Verilog.
4 bit divider design using first divider algorithm
PWM module using verilig HDL in XILINX ISE
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