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tharunchitipolu/RISC-V-32I-based-core-with-Advanced-Extensible-Interface

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5_stage_pipeline.cache

5_stage_pipeline.cache

 
 

5_stage_pipeline.hw

5_stage_pipeline.hw

 
 

5_stage_pipeline.sim/sim_1/behav/xsim

5_stage_pipeline.sim/sim_1/behav/xsim

 
 

5_stage_pipeline.srcs/sources_1/new

5_stage_pipeline.srcs/sources_1/new

 
 

pipeline_trial1_behav.wcfg

pipeline_trial1_behav.wcfg

 
 

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5 stage pipelined RISC-V core with AXI3 bus protocol between the directly mapped cache and main memory.

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arm pipeline cache processor verilog systemverilog computer-architecture testbench verilog-hdl risc-v digitaldesign axi3
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