FPGA_Slot_Machine(Top level design in Toplevel.sv)

A slot machine created in System Verilog. It was built, simulated, synthesized, and implemented in Vivado, on the Xilinx Basys 3 board.

This is my final project for my first Digital Design class as a freshman EE at Cal Poly.

I enjoyed the class a lot, and can picture myself doing more stuff like this for a career.

Name		Name	Last commit message	Last commit date
Latest commit History 10 Commits
Constraints.sv		Constraints.sv
PseudoRNG.sv		PseudoRNG.sv
README.md		README.md
TopLevel.sv		TopLevel.sv
clockdivider.sv		clockdivider.sv

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