EDAV: Open-Source EDA Viewer; render design LEF/DEF files in your browser!
-
Updated
Jan 6, 2023 - JavaScript
EDAV: Open-Source EDA Viewer; render design LEF/DEF files in your browser!
This repository contains scripts that I create through my digital design course in Verilog, VHDL, SystemVerilog etc..
Very simple Cortex-M1 SoC design based on ARM DesignStart
RTL Design and Synthesis Workshop using Verilog with Sky130 Technology
Repository containing the code for implementing the classic game Pong on a Nexys A7 Digilent FPGA development board.
A repo to store the coursework I do in college! 🎓
5 stage pipelined RISC-V core with AXI3 bus protocol between the directly mapped cache and main memory.
IP Module For LTC2311 ADC
RTL Designs along with testbenches to verify them written in Verilog. Icarus Verilog an open source simulator was used for simulations.
Educational repo for storing my practice sessions with digital systems as well as solutions to online courses or university courses I take. These implementations are done in VHDL or Verilog.
FIFO buffer library. Written and verified in SystemVerilog. Can be synthetised in ASIC or FPGA.
a quick interface to any digital device that features magazines as a product
For all the fidget spinneteers out there
Took a module on Digital Design Fundamentals during my year 2 of my undergraduate studies of Electronic Circuits done using VHDL and Verilog, with a final project on FPGA Programmed Flappy Bird Gaming System using Sound and Light effects.
A slot machine created in System Verilog. It was built, simulated, synthesized, and implemented in Vivado, for use on the Xilinx Basys 3 board.
Digital Design Timing Constraints
Basic digital lock system for safes, employing logic gates 🔐
Miscellaneous stuff from the NDSU Digital Design Class
Add a description, image, and links to the digitaldesign topic page so that developers can more easily learn about it.
To associate your repository with the digitaldesign topic, visit your repo's landing page and select "manage topics."