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38 Open 304 Closed
38 Open 304 Closed
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Issues list

Is there any interface to flush L2 Cache data feature request Feature request to be considered
#2934 opened Apr 28, 2024 by Phantom1003
1
How are the uncacheable and non-indempotent stores are handled? question Question requiring answer
#2903 opened Apr 19, 2024 by XubsXubs
@linjuanZ
3
Simulation hangs for longer running functions using the vector extension bug report Bugs to be confirmed
#2890 opened Apr 16, 2024 by camel-cdr
5
Using XiangShan to reproduce the example code in RISC-V Architecture Programming and Practice. question Question requiring answer
#2886 opened Apr 16, 2024 by Danling-droid
6 tasks done
@cebarobot
6
How to use profile function of verilator in XiangShan environment question Question requiring answer
#2858 opened Apr 8, 2024 by guyandeli
6 tasks done
6
TLB Timing interface not match with MMIO instruction fetch in IFU bug Confirmed bugs
#2658 opened Jan 18, 2024 by euphgh
1
Is there a performance visulation tool, or pipe viewer tool available?
#2646 opened Jan 16, 2024 by tariqkurd-repo
1
Non-Canonical NaN Representation in Double-Precision Results from fmadd.d Instruction
#2642 opened Jan 15, 2024 by youzi27
@huxuan0307
8
TileLink to CHI
#2630 opened Jan 11, 2024 by changekkk
3
issue about kunminghu
#2606 opened Jan 2, 2024 by menglinhan
4
L1D Cache Side-channal on Nanhu security Some designs may introduce security issues
#2534 opened Dec 7, 2023 by nieeka
1
About the Use of TL-Test
#2481 opened Nov 15, 2023 by changekkk
6
Question about debug mode on branch nanhu help wanted Extra attention is needed question Question requiring answer
#2317 opened Sep 20, 2023 by HUA-FENG1995
@huxuan0307
20
Dual-core simulation failed
#2179 opened Jul 13, 2023 by JackyWu526
1
vcs simulation throw an error
#2178 opened Jul 12, 2023 by swanger
10
How to modify the reset address and stack address space of coremark and dhrystone in nexus-am/apps?
#2143 opened Jun 21, 2023 by HUA-FENG1995
6
How to verify XSTop.v on FPGA
#2114 opened May 31, 2023 by Chiwawachiwawa
8
Is a Store Operation permitted between lr and sc?
#2069 opened May 5, 2023 by kl123s
@AugustusWillisWang
2
Question about the continuous LR instruction covering problem
#2068 opened May 5, 2023 by kl123s
@AugustusWillisWang
1
How does the dma port keep L3Cache consistent when the peripheral updates the DDR data?
#2003 opened Mar 27, 2023 by qqjinger
1
It is said that Xiangshan has successfully launched X Window. Is there an FPGA project for download reference as well as a companion bin file.
#1971 opened Mar 16, 2023 by trueif
4
Question about Tilelink consistency question Question requiring answer
#1945 opened Feb 27, 2023 by yqqfunny
1
Question about virtual address forwarding failure mentioned in LDQ question Question requiring answer
#1915 opened Feb 13, 2023 by Heresyrac
@AugustusWillisWang
7
Dockerfile is prefered for building developing environment
#1870 opened Jan 3, 2023 by backyes
2
Memory access unit optimization points enhancement New feature in plan
#1808 opened Oct 22, 2022 by AugustusWillisWang
9 tasks
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