How does the dma port keep L3Cache consistent when the peripheral updates the DDR data?

[qqjinger]

您好：
在香山SoC Integration文档中看到（链接为https://xiangshan-doc.readthedocs.io/zh_CN/latest/integration/soc/）：
256-bit AXI DMA Port: for peripherals to access CPU/DDR (CPU is the slave)
Address space: DDR space (0x8000_0000 to 0xf_ffff_ffff)
This DMA port allows the peripherals to access DDR under coherency with the CPU caches. They can send standard AXI aw/w/ar requests to this port to write/read the DDR. Memory coherency is supported in the DMA port by the L3 cache. No explicit action is needed to sync the data with CPU.
很好奇dma端口如何让外设更新ddr数据时，让L3Cache保持一致性？是需要将外设通过dma端口读写L3cache，这样间接访问DDR吗（外设->dma port -> L3 cache -> mem port -> ddr）？我理解外设更新ddr空间数据，要保持数据一致性，连接图如下，不知道理解是否正确？

[wakafa1]

您画的连接图没有问题. 香山的地址空间分为 cached 和 uncached，仅 cached 空间会进入 cache hierarchy.
对于 uncached 空间，所有的操作都是原子的，不存在一致性问题；
对于 cached 空间，外设会通过 dma 端口访问 l3cache，由其负责维护 cache hierarchy 的一致性，并能间接访问 DDR

[TRANSLATION]
There is no problem with the connection diagram you drew. The address space of Xiangshan is divided into cached and uncached, and only the cached space will enter the cache hierarchy.

For uncached Spaces, all operations are atomic and there are no consistency issues;

For cached space, the peripheral accesses the l3cache through the dma port, which is responsible for maintaining cache hierarchy consistency and can indirectly access the DDR