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vcs simulation throw an error #2178

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swanger opened this issue Jul 12, 2023 · 10 comments
Open

vcs simulation throw an error #2178

swanger opened this issue Jul 12, 2023 · 10 comments

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@swanger
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swanger commented Jul 12, 2023 •
edited by biquanha 

 ./simv

Note-[RT_BS] Larger stack needed
  Note: Bumping stack limit from 8192 to 8220 Kbytes.

Chronologic VCS simulator copyright 1991-2016
Contains Synopsys proprietary information.
Compiler version L-2016.06_Full64; Runtime version L-2016.06_Full64;  Jul 12 17:25 2023
isWriteFetchToIBufferTable0 = 0
isWriteIfuWbToFtqTable0 = 0
isWriteFTQTable0 = 0
isWriteL2TlbPrefetchTable0 = 0
isWriteL1TlbTable0 = 0
isWritePageCacheTable0 = 0
isWritePTWTable0 = 0
isWriteL2TlbMissQueueTable0 = 0
isWriteBankConflictTable0 = 0
isWriteL1MissQMissTable0 = 0
isWriteLoadMissTable0 = 0
isFirstHitWrite0 = 0
ColdDownThreshold_0 = 0
isWriteInstInfoTable0 = 0
simv compiled at Jul 12 2023, 14:26:29
The image is ram.bin
Using simulated 8192MB RAM
Using simulated 32768B flash
[warning]no valid flash bin path, use preset flash instead
--diff is not given, try to use $(NEMU_HOME)/build/riscv64-nemu-interpreter-so by default
NemuProxy using /home/wanghairun/Projects/xs-env/NEMU/build/riscv64-nemu-interpreter-so
The first instruction of core 0 has commited. Difftest enabled. 
[NEMU] Can not find flash image: (null)
[NEMU] Use built-in image instead
[src/device/io/mmio.c:38,add_mmio_map] Add mmio map 'flash' at [0x0000000010000000, 0x00000000100fffff]
No instruction of core 0 commits for 15000 cycles, maybe get stuck
(please also check whether a fence.i instruction requires more than 15000 cycles to flush the icache)
Let REF run one more instruction.
sh: spike-dasm: command not found

============== Commit Group Trace (Core 0) ==============
commit group [00]: pc 00800026a8 cmtcnt 2
commit group [01]: pc 0080002612 cmtcnt 1
commit group [02]: pc 0080002616 cmtcnt 1
commit group [03]: pc 008000261a cmtcnt 2
commit group [04]: pc 0080002622 cmtcnt 2
commit group [05]: pc 008000233a cmtcnt 1
commit group [06]: pc 00800026aa cmtcnt 1 <--
commit group [07]: pc 0080001d22 cmtcnt 2
commit group [08]: pc 0080001d26 cmtcnt 1
commit group [09]: pc 008000232e cmtcnt 1
commit group [10]: pc 0080002330 cmtcnt 2
commit group [11]: pc 008000268a cmtcnt 1
commit group [12]: pc 008000268e cmtcnt 1
commit group [13]: pc 0080002690 cmtcnt 2
commit group [14]: pc 0080002698 cmtcnt 2
commit group [15]: pc 00800026a0 cmtcnt 2

============== Commit Instr Trace ==============
commit inst [00]: pc 0080001d1e inst 0b913423 wen 0 dst 00000008 data 00000000800026f0 robidx 000000 sqidx 000000
commit inst [01]: pc 0080001d20 inst 0ba13023 wen 0 dst 00000000 data 00000000800026f0 robidx 000001 sqidx 000001
commit inst [02]: pc 0080001d22 inst 09b13c23 wen 0 dst 00000018 data 00000000800026f0 robidx 000002 sqidx 000002
commit inst [03]: pc 0080001d24 inst 00a12e23 wen 0 dst 0000001c data 00000000800026f0 robidx 000003 sqidx 000003
commit inst [04]: pc 0080001d26 inst 608000ef wen 1 dst 00000001 data 0000000080001d2a robidx 000004             
commit inst [05]: pc 008000232e inst ff010113 wen 1 dst 00000002 data 000000008000cee0 robidx 000005             
commit inst [06]: pc 0080002330 inst 00113423 wen 0 dst 00000008 data 00000000800026f0 robidx 000006 sqidx 000004
commit inst [07]: pc 0080002332 inst 358000ef wen 1 dst 00000001 data 0000000080002336 robidx 000007             
commit inst [08]: pc 008000268a inst 400017b7 wen 1 dst 0000000f data 0000000040001000 robidx 000008             
commit inst [09]: pc 008000268e inst 0007a783 wen 1 dst 0000000f data 0000000000000000 robidx 000009 (skip) lqidx 000000
commit inst [10]: pc 0080002690 inst 0107d71b wen 1 dst 0000000e data 0000000000000000 robidx 00000a             
commit inst [11]: pc 0080002694 inst 00002697 wen 1 dst 0000000d data 0000000080004694 robidx 00000b             
commit inst [12]: pc 0080002698 inst 38e6a823 wen 0 dst 00000010 data 00000000800026aa robidx 00000c sqidx 000005
commit inst [13]: pc 008000269c inst 0807c7bb wen 1 dst 0000000f data 0000000000000000 robidx 00000d             
commit inst [14]: pc 00800026a0 inst 00002717 wen 1 dst 0000000e data 00000000800046a0 robidx 00000e             
commit inst [15]: pc 00800026a4 inst 38f72023 wen 0 dst 00000000 data 00000000800026aa robidx 00000f sqidx 000006
commit inst [16]: pc 00800026a8 inst 00008067 wen 0 dst 00000000 data 00000000800026aa robidx 000010             
commit inst [17]: pc 0080002336 inst 2dc000ef wen 1 dst 00000001 data 000000008000233a robidx 000011             
commit inst [18]: pc 0080002612 inst 3800c7b7 wen 1 dst 0000000f data 000000003800c000 robidx 000012             
commit inst [19]: pc 0080002616 inst ff87b783 wen 1 dst 0000000f data 000000000000000e robidx 000013 (skip) lqidx 000001
commit inst [20]: pc 008000261a inst 080787bb wen 1 dst 0000000f data 000000000000000e robidx 000014             
commit inst [21]: pc 008000261e inst 00002717 wen 1 dst 0000000e data 000000008000461e robidx 000015             
commit inst [22]: pc 0080002622 inst 3ef73d23 wen 0 dst 0000001a data 0000000080002628 robidx 000016 sqidx 000007
commit inst [23]: pc 0080002626 inst 00008067 wen 0 dst 00000000 data 0000000080002628 robidx 000017             
commit inst [24]: pc 008000233a inst 370000ef wen 1 dst 00000001 data 000000008000233e robidx 000018             
commit inst [25]: pc 00800026aa inst 00008067 wen 0 dst 00000000 data 00000000800026ac robidx 000019              <--
commit inst [26]: pc 0080001d12 inst 0d313c23 wen 0 dst 00000018 data 00000000800026f0 robidx 00001a sqidx 000006
commit inst [27]: pc 0080001d14 inst 0d413823 wen 0 dst 00000010 data 00000000800026f0 robidx 00001b sqidx 000007
commit inst [28]: pc 0080001d16 inst 0d513423 wen 0 dst 00000008 data 00000000800026f0 robidx 00001c sqidx 000008
commit inst [29]: pc 0080001d18 inst 0d613023 wen 0 dst 00000000 data 00000000800026f0 robidx 00001d sqidx 000009
commit inst [30]: pc 0080001d1a inst 0b713c23 wen 0 dst 00000018 data 00000000800026f0 robidx 00001e sqidx 00000a
commit inst [31]: pc 0080001d1c inst 0b813823 wen 0 dst 00000010 data 00000000800026f0 robidx 00001f sqidx 00000b

==============  REF Regs  ==============
  $0: 0x0000000000000000   ra: 0x0000000080001d2a   sp: 0x000000008000cee0   gp: 0x0000000000000000 
  tp: 0x0000000000000000   t0: 0x0000000080000000   t1: 0x0000000000000000   t2: 0x0000000000000000 
  s0: 0x0000000000000000   s1: 0x0000000000000000   a0: 0x0000000080003f1d   a1: 0x0000000000000000 
  a2: 0x0000000000000000   a3: 0x0000000080004694   a4: 0x000000008000461e   a5: 0x000000000000000e 
  a6: 0x0000000000000000   a7: 0x0000000000000000   s2: 0x0000000000000000   s3: 0x0000000000000000 
  s4: 0x0000000000000000   s5: 0x0000000000000000   s6: 0x0000000000000000   s7: 0x0000000000000000 
  s8: 0x0000000000000000   s9: 0x0000000000000000  s10: 0x0000000000000000  s11: 0x0000000000000000 
  t3: 0x0000000000000000   t4: 0x0000000000000000   t5: 0x0000000000000000   t6: 0x0000000000000000 
 ft0: 0xffffffff7f800000  ft1: 0x0000000000000000  ft2: 0xb1a5e263b1a5e263  ft3: 0x7d0aa1fa7d0aa1fa 
 ft4: 0xf8b48ef1f8b48ef1  ft5: 0x5b5cd7b65b5cd7b6  ft6: 0x463c8f8c463c8f8c  ft7: 0xdf6afebedf6afebe 
 fs0: 0x554ff5aa554ff5aa  fs1: 0x531a33a6531a33a6  fa0: 0x0000000000000000  fa1: 0xf2da72e5f2da72e5 
 fa2: 0x023d0b04023d0b04  fa3: 0xed73c6daed73c6da  fa4: 0xcbf2e297cbf2e297  fa5: 0x8864621088646210 
 fa6: 0xb15a2c62b15a2c62  fa7: 0xc49f8289c49f8289  fs2: 0x0ef6411d0ef6411d  fs3: 0xbc5f5678bc5f5678 
 fs4: 0x0511770a0511770a  fs5: 0x6701d5ce6701d5ce  fs6: 0x66fc7fcd66fc7fcd  fs7: 0xc6a89e8dc6a89e8d 
 fs8: 0x4274c5844274c584  fs9: 0xe813e6d0e813e6d0 fs10: 0xbf49d47ebf49d47e fs11: 0xbff0467fbff0467f 
 ft8: 0x2b19b3562b19b356  ft9: 0x818fa403818fa403 ft10: 0xaebc3e5daebc3e5d ft11: 0xb9c51673b9c51673 
pc: 0x0000000080002340 mstatus: 0x8000000a00006000 mcause: 0x0000000000000000 mepc: 0x86a9720d86a9720c
                       sstatus: 0x8000000200006000 scause: 0x0000000000000000 sepc: 0x0000000000000000
satp: 0x0000000000000000
mip: 0x0000000000000000 mie: 0x0000000000000000 mscratch: 0x0000000000000000 sscratch: 0x0000000000000000
mideleg: 0x0000000000000000 medeleg: 0x0000000000000000
mtval: 0x0000000000000000 stval: 0xac28c658ac28c658 mtvec: 0x0000000000000000 stvec: 0x0000000000000000
privilege mode:3  pmp: below
 0: cfg:0x00 addr:0x0000000000000000| 1: cfg:0x00 addr:0x0000000000000000
 2: cfg:0x00 addr:0x0000000000000000| 3: cfg:0x00 addr:0x0000000000000000
 4: cfg:0x00 addr:0x0000000000000000| 5: cfg:0x00 addr:0x0000000000000000
 6: cfg:0x00 addr:0x0000000000000000| 7: cfg:0x00 addr:0x0000000000000000
 8: cfg:0x00 addr:0x0000000000000000| 9: cfg:0x00 addr:0x0000000000000000
10: cfg:0x00 addr:0x0000000000000000|11: cfg:0x00 addr:0x0000000000000000
12: cfg:0x00 addr:0x0000000000000000|13: cfg:0x00 addr:0x0000000000000000
14: cfg:0x00 addr:0x0000000000000000|15: cfg:0x00 addr:0x0000000000000000
priviledgeMode: 3
$finish called from file "/home/wanghairun/Projects/xs-env/XiangShan/difftest/src/test/vsrc/vcs/top.v", line 152.
$finish at simulation time                33235
           V C S   S i m u l a t i o n   R e p o r t 
Time: 33235 ns
CPU Time:     41.830 seconds;       Data structure size:  66.5Mb

请问一下，这个vcs仿真是已经跑起来了吗？为什么用的默认的ready-to-run目录下的coremark case会报错？

谢谢！

[TRANSLATION]
Excuse me, is this vcs simulation running? Why does the default coremark case in the ready-to-run directory throw an error?
@wakafa1
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wakafa1 commented Jul 13, 2023 •
edited by biquanha

请提供一下 VCS 仿真的香山版本，我们这边复现检查一下

[TRANSLATION]
Please provide the Xiangshan version of VCS simulation, we will repeat and check it

@swanger
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swanger commented Jul 14, 2023

git submodule
ca590e7 coupledL2 (pass-dualcore-tl-test-92-gca590e7)
0a1e5e2 difftest (heads/master)
43474be4c76bb0afe3b2d8358e26f3c37c38b380 fudian (remotes/origin/fadd-adjust-7-g43474be)
b7308d958dfa7073e47ca10ce3974d267592049c huancun (remotes/origin/nanny-9-gb7308d9)
ff39f3680f69f9b38fa3cdf4c9fc1b2c6b3ec919 ready-to-run (remotes/origin/nanhu-pmp-fix-2-gff39f36)
254ebf7150e1d633fee123281f723d9936d30075 rocket-chip (remotes/origin/xs-merge-41-g254ebf715)
3d812fec9936ccd584df7721aa8c2d02e932d325 utility (remotes/origin/fix-chiseldb)

git log
commit a483ee0 (HEAD -> master, origin/master, origin/HEAD)
Author: Guokai Chen chenguokai17@mails.ucas.ac.cn
Date: Thu Jul 6 13:08:00 2023 +0800

Predecode: fix unintended width cast (#2150)

...

@wakafa1
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wakafa1 commented Jul 17, 2023 •
edited by biquanha

我们按照你提供的代码版本运行了 vcs 仿真，无法复现问题，请再仔细检查运行流程。可以贴一下你执行的所有命令

[TRANSLATION]
We ran the vcs simulation according to the code version you provided, but the problem could not be reproduced. Please carefully check the running process again. You can post all the commands you executed

@ppx-bit
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ppx-bit commented Jul 17, 2023 •
edited

@wakafa1

sh: spike-dasm: command not found

log文件中，为何会出现该该命令未能找到？

@wakafa1
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wakafa1 commented Jul 17, 2023

这是 Spike 项目提供的一个机器码转汇编的工具，可以参考 https://github.com/riscv-software-src/riscv-isa-sim
如果没有安装也不会影响仿真结果

@ppx-bit
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ppx-bit commented Jul 17, 2023 •
edited by biquanha

好的。
XiangShan仓库里面只有Verilator以及VCS相关的Makefile文件。
Xiangshan是否只支持vcs而不支持xrun？

[TRANSLATION]
Well.

The only Makefiles in the XiangShan repository are Verilator and VCS.

Does Xiangshan support only vcs but not xrun?

@wakafa1
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wakafa1 commented Jul 17, 2023 •
edited by biquanha

香山目前支持 Verilator 和 VCS，暂不支持 xrun

[TRANSLATION]
Xiangshan currently supports Verilator and VCS, but does not support xrun

@ppx-bit
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ppx-bit commented Jul 17, 2023 •
edited by biquanha

目前我正在使用xrun运行XiangShan项目，但是中间出现了一些问题，其中一个和该issue一样。

能否告知一下，你们项目组不支持xrun的理由吗？
是由于xrun的特性不支持XiangShan项目；还是由于你们并没有去开发相关的xrun mk。
如果是后者，后续我本地跑通后，可以将相关的mk上传到该仓库。

[TRANSLATION]
I am currently running the XiangShan project using xrun, but there are some issues, one of which is the same as this issue.

Could you tell me the reason why your project team does not support xrun?

Because xrun doesn't support the XiangShan project. Or because you didn't develop the xrun mk.

If it is the latter, I can upload the relevant mk to the repository after I get through the local run.

@wakafa1
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wakafa1 commented Jul 17, 2023 •
edited by biquanha

我们目前暂时没有做 xrun 的适配，欢迎你给香山贡献代码

[TRANSLATION]
We have not done xrun adaptation at present, you are welcome to contribute code to Xiangshan

@ppx-bit
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ppx-bit commented Jul 31, 2023

@swanger 你好，请问这个问题后续你是怎么解决的？

@Tang-Haojin Tang-Haojin changed the title vcs 仿真报错 vcs simulation throw an error Dec 27, 2023
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@swanger @wakafa1 @ppx-bit