How are the uncacheable and non-indempotent stores are handled?

[XubsXubs]

Hi, to the developers of XiangShan,

My question is as in the title, I have seen there is a module named PATH/dcache/Uncache.scala, which mentioned uncacheable load and stores, and this is instantiated in the backend/memblock.scala as show here:
private val dcache = outer.dcache.module
val uncache = outer.uncache.module
switch (uncacheState) {
is (s_idle) {
when (uncacheReq.fire) {
when (lsq.io.uncache.req.valid) {
val isStore = lsq.io.uncache.req.bits.cmd === MemoryOpConstants.M_XWR
when (!isStore || !io.ooo_to_mem.csrCtrl.uncache_write_outstanding_enable) {
uncacheState := s_scalar_uncache
}
....
}
Then the store is removed from this.
As this also did not show up on the diagrams in slides, so could you help with this?

[linjuanZ]

The code you quote means that if this request is a load, or a store that is not allowed to be outstanding, LSU should wait for response from uncache until the next request is accepted.

[XubsXubs]

I read on the document that, for MMIO ld, for example, it is maintained in the load queue until it reaches the head of ROB, then it would be sent to the downwards; same seems to be for the MMIO store, that needs to wait for becoming the head of ROB, then can be send to downwards.

What is the connection here, are the Uncache relevant here?

[linjuanZ]

I read on the document that, for MMIO ld, for example, it is maintained in the load queue until it reaches the head of ROB, then it would be sent to the downwards; same seems to be for the MMIO store, that needs to wait for becoming the head of ROB, then can be send to downwards.

What is the connection here, are the Uncache relevant here?

Uncache is a module that receives mmio loads/stores from LSQ and transforms the requests to TileLink messages.