How to verify XSTop.v on FPGA

[Chiwawachiwawa]

你好，請問如果我獲得了 XSTop.v 文件之後，我下一步該如何在 FPGA 上面進行驗證呢。
我目前是開了一個 vivado 的專案，並且新增了一個 block designs，目前的思路為添加了XSTop.v之後將一些外設補齊，但是我發現我沒有辦法將 XSTop.v 加入到我的設計之中，想請問我該如何解決，亦或是我的方向與步驟做錯了，需要做額外的準備，感謝你!

[TRANSLATION]
Hello, could you please tell me how to perform verification on the FPGA after I get the XSTop.v file?

At present, I have opened a vivado project and added a new block designs. The current idea is to add XSTop.v and then fill in some peripherals, but I find that I can not add XSTop.v to my design, would you please tell me how to solve it? Or I have done the wrong direction and steps, and need to do extra preparation, thank you!

[wakafa1]

XSTop.v 作为香山处理器核的 RTL 代码，还需要搭建一版 SoC 才能在 FPGA 上进行验证；SoC 需要支持的内容包括但不限于 DDR 控制器、中断连线、各类外设比如串口等

[TRANSLATION]
As the RTL code of Xiangshan processor core, XSTop.v needs to build a version of SoC to be verified on FPGA. SoC support includes, but is not limited to, DDR controllers, interrupts, and various peripherals such as serial ports

[Chiwawachiwawa]

感謝回復!那請問香山生成的東西，我只需要將 XSTop.v 加入vivado 專案之中，其他外設自行定義，還是需要添加其他生成的資源呢(我嘗試把整個 build 拉進專案之中，結果vivado跑不太動)?

[TRANSLATION]
Thanks for the reply! I only need to add XSTop.v to the vivado project, and define other peripherals by myself, or do I need to add other generated resources (I tried to pull the whole build into the project, but vivado didn't work very well)?

[wakafa1]

还有一些 array 开头的 verilog 文件也需要包含在内；
另外需要注意，生成出来的 verilog 可能有部分不可综合的代码，请手动把 DebugOptions 中的 AlwaysBasicDiff 参数设置为 false

[TRANSLATION]
There are also some verilog files that start with arrays that need to be included;

Also note that some of the generated verilog code may not be synthesizable, so manually set the AlwaysBasicDiff parameter in DebugOptions to false

[Chiwawachiwawa]

了解了，感謝你的細心回復!有遇到問題還要再麻煩了!

[TRANSLATION]
I see. Thank you for your careful reply! Have encountered the problem even again trouble!

[Chiwawachiwawa]

请手动把 DebugOptions 中的 AlwaysBasicDiff 参数设置为 false

不好意思，請問是 vivado 之中的選項嗎(? 我在2022.2的版本中沒有找到

[Tang-Haojin]

是香山的参数，请参见这一行代码。

[TRANSLATION]
Is the parameter of Fragrant hill, see [this line of code]

[Chiwawachiwawa]

你好，修改完後依舊有錯誤的檔案，大多為sim相關的

[TRANSLATION]
Hello, there are still wrong files after modification, most of them are SIM-related

[wakafa1]

请提供更加详细的信息以便我们判断