openlane
Here are 28 public repositories matching this topic...
Report of the contents learned in the 5-day workshop by VSD regarding the open-source EDA tools in the VLSI industry
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Feb 25, 2021
This repository documents my work on Advanced Physical Design Using OpenLANE/Sky130. The objective of this project was to implement an opensource RTL2GDS flow using OpenLANE and opensource PDK provided by Google/SkyWater130
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Jul 7, 2021
Gate-level visualization generator for SKY130-based chip designs.
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Jul 22, 2021 - Python
CLEAR is an Open Source FPGA ASIC delivered to you on its development board and its open source software development tools and all the ASIC design tools used to create it.
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Mar 19, 2022 - Verilog
Digitally synthesizable architecture for SerDes using Skywater Open PDK 130 nm technology.
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Mar 26, 2022 - Verilog
This is part of EC383 - Mini Project in VLSI Design.
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May 8, 2022 - Verilog
This project give overview of RTL to GDSII of universal shift register using OpenLane and Skywater130 PDK. OpenLane is an automated open-source EDA tool which gives RTL to GDSII flow.
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Jul 19, 2022 - Verilog
Creating this repo to document the learnings from the workshop Advanced Physical Design using OpenLANE/SKY130 conducted by VSD
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Aug 7, 2022
Documentation for the 5 day workshop: Advanced Physical Design using OpenLane/Sky130
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Sep 17, 2022
This repository is dedicated to VLSI ASIC Design Flow using open-source tools! Here, we embark on a journey that starts with specifications, RTL DV, Synthesis, Physical Design, Signoff and Finally Tape-It-Out
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Jan 23, 2024 - Verilog
Picorv32-IM with exact and approximate SIMD multiplication extensions. The SIMD modules can be accessed with custom RISC-V Instruction to perform dual/quad 8-bit multiplications.
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Jan 28, 2024 - Verilog
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