A really fast, secure random file generator. Much faster than /dev/urandom.

PrySec - Privacy & Security framework for your .NET applications

Peat, a Python-based Intel-Optimized Tensorflow dockerization with CPU & Memory constraints configurator

Learned Approximate Matrix Profile (LAMP) implementation on Ultra96-v2 board

An Optimal Microarchitecture for Stencil Computation Acceleration Based on Nonuniform Partitioning of Data Reuse Buffers on FPGAs

This repository contains the findings for scheduling heterogeneous payloads within the Distributed Unit (DU) of a 5G Radio Access Network (RAN)

Aureal A3D Software Development Kit

An open-source parameterizable NPU generator with full-stack multi-target compilation stack for intelligent workloads.

Verilog implementation of an ordinary differential equation (ODE) solver accelerator chip ― **INCOMPLETE IMPLEMENTATION**

Hardware Accelerator design for Euler and Modified method in solving ODE using VHDL language in Xilinx Vivado Environment

grayscale conversion system and simple convolution system

Innervator: Hardware Acceleration for Artificial Neural Networks in FPGA using VHDL.

Working 8x8 systolic array hardware implemented in Xilinx Vivado, operated and controlled in software using Xilinx Vitis

A collection of WebGPU samples.

Machine Vision Cam Landing Page

A configurable processing element for deep neural network accelerators

Open source RTL simulation acceleration on commodity hardware

A neural network fast inference library implementing Coral Edge TPU emulator using AVX2.

This framework was part of the Diploma thesis titled "Architectures and Implementations of the Neural Network LeNet-5 in FPGAs". The main goal of this thesis was to create a LeNet-5 implementation in an FPGA development board, but also form a reusable framework/workflow which can be modified to model and develop other Neural Networks as well.