Skip to content
View jracevedob's full-sized avatar
:octocat:
I may be slow to respond.
:octocat:
I may be slow to respond.
11 followers · 86 following

Achievements

Achievement: Pull Shark
BetaSend feedback

Achievements

Achievement: Pull Shark
BetaSend feedback

Highlights

Block or Report

Block or report jracevedob

Block user

Prevent this user from interacting with your repositories and sending you notifications. Learn more about blocking users.

You must be logged in to block users.

Please don't include any personal information such as legal names or email addresses. Maximum 100 characters, markdown supported. This note will be visible to only you.
Report abuse

Contact GitHub support about this user’s behavior. Learn more about reporting abuse.

Report abuse
jracevedob/README.md

Javier Acevedo

I am professional baseband system engineer in Dresden, Germany. I am mostly interested on designing and deploying versatile and agile state-of-the-art compute platforms for wireless communication systems. I am currently working on bringing hardware acceleration to the Radio Access Network (RAN), while integrating it with the Core Network.

Motto

It is better to die on your feet that live on your knees - Emiliano Zapata.

Main functional motivation

Hardware-Software Co-Design of the entire product development life cycle for 5G's RAN and Core Network.

Contact

You can contact me mainly via E-mail under the following address or Twitter account.

Current projects

In this moement, we are working on two different projects about wireless communications and genetics.

  1. Hardware accelerated version of the Open RAN Intelligent Controller (RIC).
  2. Hardware accelerated version of the training sequence for protein folding. ESM Meta

Popular repositories

  1. Post-Shannon-SDR Post-Shannon-SDR Public

    In this repository, you will find the source code for analyzing tracks during data transmission using Software Defined Radios. Metrics about error positioning and error syndrome are attached.

    Python 7 1

  2. Processor-Design Processor-Design Public

    In this repository, it is presented the whole design of a functional RISC processor. Therefore, the design of every functional block (arithmetic and control units among others) is written in Verilo…

    Verilog 4

  3. MPSoC_Networking MPSoC_Networking Public

    This repository contains the source code for implementing data exchange through the SFP+ Cages of the Xilinx's Multi-processor System-on-Chip (MPSoC)

    VHDL 2

  4. composite_finite_fields composite_finite_fields Public

    In this directoy, you will find a composite finite field calculator for different matrix sizes. The default matrix size will deal with Galois fields GF(2), but the calculation will scale up to infi…

    C 1

  5. OrchestRAN OrchestRAN Public

    This repository contains the findings for scheduling heterogeneous payloads within the Distributed Unit (DU) of a 5G Radio Access Network (RAN)

    1

  6. vRU vRU Public

    In this repository, you will find the virtualization of the Radio Unit for the 5G Radio Access Networks.

    1