RTL Designs along with testbenches to verify them written in Verilog. Icarus Verilog an open source simulator was used for simulations.
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Updated
Aug 25, 2022 - Verilog
RTL Designs along with testbenches to verify them written in Verilog. Icarus Verilog an open source simulator was used for simulations.
IP Module For LTC2311 ADC
Educational repo for storing my practice sessions with digital systems as well as solutions to online courses or university courses I take. These implementations are done in VHDL or Verilog.
FIFO buffer library. Written and verified in SystemVerilog. Can be synthetised in ASIC or FPGA.
a quick interface to any digital device that features magazines as a product
For all the fidget spinneteers out there
Took a module on Digital Design Fundamentals during my year 2 of my undergraduate studies of Electronic Circuits done using VHDL and Verilog, with a final project on FPGA Programmed Flappy Bird Gaming System using Sound and Light effects.
A slot machine created in System Verilog. It was built, simulated, synthesized, and implemented in Vivado, for use on the Xilinx Basys 3 board.
Digital Design Timing Constraints
Basic digital lock system for safes, employing logic gates 🔐
Miscellaneous stuff from the NDSU Digital Design Class
PWM module using verilig HDL in XILINX ISE
This repository contains a few useful Verilog modules
4 bit divider design using first divider algorithm
Школа инженера от DigitalDesign
This repository contains different modules which execute arithmetic operations.
RTL Design and Synthesis Workshop using Verilog with Sky130 Technology
Repository containing the code for implementing the classic game Pong on a Nexys A7 Digilent FPGA development board.
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