verilog-programs

Here are 24 public repositories matching this topic...

neelkshah / MIPS-Processor

5-stage pipelined 32-bit MIPS microprocessor in Verilog

verilog microprocessor computer-architecture microprocessors verilog-hdl mips-architecture mips-processor bits-pilani computer-organization verilog-components verilog-snippets mips-instructions computer-organisation verilog-programs verilog-simulator verilog-project

Updated Apr 3, 2020
Verilog

snbk001 / Verilog-Design-Examples

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Verilog Design Examples with self checking testbenches. Half Adder, Full Adder, Mux, ALU, D Flip Flop, Sequence Detector using Mealy machine and Moore machine, Number of 1s, Binary to Gray Conversion, Up down counter, Clock Divider, PIPO, n bit universal shift register, 4 bit LFSR, Single port RAM, Dual port RAM, Synchronous FIFO, Asynchronous F…

verilog testbenches verilog-hdl verilog-programs verilog-project verilog-code verilog-design self-checking

Updated Jan 29, 2024
Verilog

ashishrana160796 / verilog-starter-tutorials

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Tutorial series on verilog with code examples. Contains basic verilog code implementations and concepts.

practice embedded-systems verilog up-for-grabs circuit switches beginner-friendly logic-gates hdl verilog-hdl iverilog verilog-snippets verilog-programs verilog-project

Updated Nov 25, 2020
Verilog

Arjun-Narula / Traffic-Light-Controller-using-Verilog

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the project includes system design of a t intersection traffic light controller and its verilog code in vivado design suite.

traffic verilog vivado verilog-hdl traffic-light traffic-sign-recognition vivado-hls verilog-programs verilog-simulator verilog-project verilog-code vivado-simulator

Updated Jul 18, 2020
JavaScript

mihir8181 / VerilogHDL-Codes

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Synthesizable Verilog Source Codes(DUT), Test-bench and Simulation Results.

counter fsm asynchronous verilog fifo testbenches verilog-hdl verilog-programs mealy-machine-code moore-machine-code verilog-project fifo-buffer verilog-code n-bit-alu verilogvalidation design-under-test asynchronous-fifo fifo-verilog

Updated May 10, 2019
Verilog

Akashtailor-exe / 30-days-of-verilog

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30 Days of Verilog: Dive into digital circuits with a month of Verilog coding challenges. From logic gates to FSMs, sharpen your skills and simulate your designs. Let's code and conquer circuits!

verilog vlsi 30daysofcode 30-days-of-code digital-logic-design verilog-programs digitalcircuit verilog-project rtl-design rtl-coding

Updated Sep 30, 2023

sarthak268 / Embedded_Logic_and_Design

Sponsor

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This repository contains all labs done as a part of the Embedded Logic and Design course.

Updated Jun 10, 2018

pendkeomkar / SPI

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Title : Communication Bridge between I2C and SPI Platform : RTL Coding (Verilog/System Verilog/VHDL) Duration : 1 Month Description : Both SPI and I2C are robust, stable communication protocols that are widely used in today's complex systems.The I2C bus has a minimum pin count requirement and therefore a smaller footprint on the board. The SPI b…

verification verilog spi uvm verification-methodologies verilog-hdl verilog-programs verification-codes verilog-project verification-component

Updated Aug 21, 2018

Nidhinchandran47 / my_rtl_code

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Repository for RTL building blocks #100daysofrtl VERILOG VHDL System Verilog

fpga vhdl verilog hdl vlsi system-verilog verilog-hdl verilog-programs verilog-project rtl-coding

Updated Apr 1, 2024
Verilog

agneepradeep / Projects

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Welcome to my GitHub repository! Here, you'll find a diverse collection of programs implemented in Java, Python, Verilog, C, C++, and MATLAB. This repository covers a broad spectrum of topics, including data structures and algorithms, providing a valuable resource for learning and reference

python c java algorithms cpp matlab gui-application data-structures verilog-programs