basys3

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Here are 81 public repositories matching this topic...

krish1925 / Texas-Holdem-Poker

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Implementation of Texas Hold'em Poker on Verilog(Basys3 FGPA)

c poker signal-processing verilog debouncing basys3 logic-design

Updated May 11, 2024
Verilog

krish1925 / Logic-Design-Verilog

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Labwork on Logic Design implementation in Verilog on a Basys3 FPGA Module

modular verilog uart basys3 modular-design half-adder full-adder fpga-programming 7-segment-display

Updated Apr 13, 2024
Tcl

chili-chips-ba / openXC7-TetriSaraj

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Demo of how to use https://github.com/openXC7 tools (yosys+nextpnr-xilinx) to implement the HW side of a custom SoC with RISC-V CPU & our special Video Controller in Basys3 Artix7-35T. Complemented with SW in the bare-metal 'C' they, together, make for this classic game. Except that it's now, in the standard BiH tradition, with a twist of our own.

open-source gamedev fpga rtl xilinx soc verilog-hdl yosys basys3 tetris-game nextpnr xc7a35t

Updated Feb 25, 2024
Verilog

yasanthaniroshan / NanoProcessor

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A Nanoprocessor designed to run on the Basys3 FPGA desgined using Xlinx Vivado with VHD using Registers, Add/Sub Unit, Decoders, Multiplexers which have been implemented seperately.

Updated Feb 13, 2024
JavaScript

imshaaz21 / Spiking-Neural-Network-on-FPGA

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CS4362 - Hardware Description Languages. Implemented SNN on an FPGA for real-time image processing using VHDL

fpga vhdl spiking-neural-networks basys3 snn neural-network-on-fpga

Updated Dec 29, 2023
C

aliasgharchakera / flappy-bird

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The game of flappy bird coded in Verilog

fpga verilog basys3

Updated Dec 25, 2023
HTML

Shubhayu-Das / VL504-project

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Displaying images taken from an OV7670/laptop camera

uart-verilog vga basys3 ov7670

Updated Dec 15, 2023
Python

aryan-programmer / axi_stream_array_sum_microblaze

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A Vitis & Vivado project (for the Basys3 board (Atrix-7 FPGA)) that reads integers input on the switches sequentially, adds them up and displays them on the 7 segment diaplay. Demonstrates Microblaze, AXI and AXI streams.

Updated Dec 3, 2023
C

aryan-programmer / axi_gen_and_sum_primes_fpga

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A Vitis & Vivado project (for the Basys3 board (Atrix-7 FPGA)) that generates primes and sums them up over an AXI memory interface.

Updated Nov 21, 2023
TeX

redders7 / EE2026

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Multi-application FPGA project built with Verilog

fpga basys3 verilog-project

Updated Oct 30, 2023
Verilog

j3soon / Handwritten-Digit-Recognition-Painter

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A handwritten digit recognition painter implementation on Basys 3 Artix-7 FPGA using Verilog.

deep-learning hardware verilog basys3 painter artix-7

Updated Oct 29, 2023
VHDL

Gowtham1729 / Image-Processing

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Image Processing Toolbox in Verilog using Basys3 FPGA

Updated Sep 19, 2023
VHDL

SharadaShehan / Nanoprocessor_Design

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Xilinx Vivado project for nanoprocessor designing with VHDL

vhdl basys3 xilinx-vivado digital-logic-design

Updated Sep 4, 2023
VHDL

BavoDebraekeleer / fpga-dsp-visualizer

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A Digilent Basys 3 Artix-7 FPGA board project for Digital Systems Development at AP University of Applied Sciences and Arts Antwerp, by Bavo Debraekeleer

fpga dsp vhdl basys3

Updated Aug 28, 2023
VHDL

elifberaysariisik / vhdl-solar-tracker

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VHDL based solar tracker which tracks the position of the sun light

arduino fpga vhdl basys3 solartracker

Updated Aug 9, 2023

suoglu / AXI-lite-slave

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Slaves for AXI-lite interface

gpio fpga basys3 arty nexys-video axi-lite

Updated Aug 3, 2023
Tcl

prietojulii / mips_2023

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Procesador de 32 bits MIPS, operando a una frecuencia de 90.909 MHz con una arquitectura de 5 etapas. Fue desarrollado en Verilog para ser implementado en una FPGA Basys3.

engineering fpga mips processor architecture computer verilog basys3